To enable the trap handler to return a result for floating-point data register destinations,
the MPU and the FPCP supply:
1. The address of the instruction where the error occurred (in the FPIAR). By examining
the instruction, the trap handler may determine the operation being performed, the
value of the second operand (for dyadic instructions), and the destination location.
2. The exceptional operand in the FPCP idle state frame. For additional FSAVE state
frame information, refer to 6.4.2 State Frames. When an SNAN trap occurs, the ex-
ceptional operand is the source input argument converted to extended precision.
Note that the trap handler should use only the FMOVEM instruction to read or write the
floating-point data registers since FMOVEM cannot generate further exceptions or change
the condition codes.
6.1.4 Overflow
An overflow occurs when the intermediate result of an arithmetic operation is too large to
be represented in a floating-point data register using the selected rounding precision. A
store-to-memory operation overflows when the value in the source floating-point data
register is too large to be represented in the destination format.
Overflow is detected for arithmetic operations where the destination is a floating-point
data register when the intermediate result exponent is greater than or equal to the max-
imum exponent value of the selected rounding precision. (Refer to 2.2.2 FPCR Mode Control
Byte.) Overflow is detected for store-to-memory operations when the intermediate result
exponent is greater than or equal to the maximum exponent value of the destination data
format. Overflow can only occur when the destination is in the S, D, or X format. Overflows
when converting to the B, W, or L integer and packed decimal formats are included as
operand errors. Refer to 3.6 DATA FORMAT DETAILS for the maximum exponent value
for each format. At the end of any operation that could potentially overflow, the intermediate
result is checked for underflow, rounded, and checked for overflow before it is stored to
the destination. If overflow occurs, the OVFL bit is set in the FPSR exception byte.
NOTE
An overflow can occur when the destination is a floating-point data register and
the selected rounding precision is single or double even if the intermediate result
is small enough to be represented as an extended precision number. The inter-
mediate result is rounded to the selected precision (both the mantissa and the
exponent), and then the rounded result is stored in extended precision format. If
the magnitude of the intermediate result exceeds the range of the selected round-
ing precision format, an overflow occurs. The FSGLMUL and FSGLDIV instructions
are the exceptions in that, although the mantissa of the intermediate result is
rounded to single precision, the exponent remains an extended format exponent.
Therefore, those instructions can never report an overflow as long as the inter-
mediate result is small enough to be represented in extended precision format.
Trap Disabled Results:
The current rounding mode determines the value to be stored at
the destination, as follows:
MC68881/MC68882 USER'S MANUAL FREESCALE
6-9
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