6
Rounding
Mode
Result
RN
RZ
RM
RP
Infinity, with the sign of the intermediate result
Largest magnitude number, with the sign of the intermediate result
For positive overflow, largest positive number
For negative overflow, - infinity
For positive overflow, + infinity
For negative overflow, largest negative number
Trap Enabled Results:
The result stored in the destination is the same as the result stored
when the trap is disabled, and a take exception primitive is returned to the MPU. If the
destination is memory or an MPU data register, the operand is stored, and then a take
mid-instruction exception primitive is issued. If the destination is a floating-point data
register, a take exception primitive is returned when the MPU reads the response CIR of
the FPCP. Since the MC68881 does not allow multiple floating-point concurrency, a take
pre-instruction exception is reported when the MPU attempts the next floating-point in-
struction. The MC68882 can report an exception as a mid-instruction exception on a sub-
sequent floating-point instruction.
The address of the instruction that causes the overflow is available to the trap handler in
the FPIAR. By examining the instruction, the trap handler can determine the arithmetic
operation type and destination location. The trap handler can execute an FSAVE instruction
to obtain additional information. When an FSAVE is executed, the exceptional operand is
stored in the state frame. Refer to 6.4.2 State Frames for details of the FSAVE instruction
state frames. When an overflow occurs, the exceptional operand is defined differently for
various destination types:
1. Memory or MPU data register destination -- the value in the exceptional operand is
the intermediate result mantissa rounded to the destination precision, with a 15-bit
exponent biased as a normal extended precision number. In the case of a memory
destination, the evaluated effective address of the operand is available in the MPU
mid-instruction stack frame (at offset +$10). This allows the trap handler to overwrite
the default result, if necessary, without recalculating the effective address.
2, Floating-point data register destination -- the value in the exceptional operand is the
intermediate result rounded to extended precision, with an exponent bias of
$3FFF-$6000 rather than $3FFF. The additional bias of -$6000 is used to "wrap" the
17-bit intermediate value into a value that can be represented in 15 bits. To recover
the 17-bit twos-complement exponent of the intermediate result, the 15-bit exponent
of the exceptional operand should be sign extended to at least 17 bits (i.e., if it is
manipulated in an MPU
data
register, it is sign extended to a long word value), and
then the bias of $3FFF-$6000 should be subtracted from that number. Note that for
most operations, the intermediate exponent value does not exceed 32,767 end thus
can be contained in a 16-bit integer. However, a completely general exception handler
should calculate a 17-bit exponent value.
In addition to normal overflow, the exponential instructions implemented by the FPCP
(eX, 10x, 2x, SINH, COSH, and FSCALE) may generate results that overflow the 17-bit
exponent used for intermediate results. For example, the eX function can easily overflow
the 17-bit intermediate exponent if the source value is a large number (x >i +18,192).
When such an overflow occurs (called a catastrophic overflow), the exceptional op-
erand exponent value is set to $0000. This value is easily distinguished from the
exceptional operand exponent values produced by normal overflow processing. The
FREESCALE
6-10
MC68881/MC68882 USER'S MANUAL
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