of the exceptional operand is sign extended to at least 17 bits (i.e., if it is manipulated
in an MPU data register, it is sign extended to a long-word value), and then the bias
of $3FFF+ $6000 is subtracted from that number. Note that for most operations, the
intermediate exponent value is not less than -32,768, and thus can be contained in
a 16-bit integer. However, a completely general exception handler should calculate a
17-bit exponent value.
In addition to normal underflow, the exponential instructions implemented by the
FPCP (ex, 10x, 2x, SINH, COSH, and FSCALE) may generate results that underflow
the 17-bit exponent used for intermediate results. For example, the ex function can
easily underflowthe 17-bit intermediate exponent if the source value is a large number
(x ~< -8,192). When such an underfiow occurs (called a catastrophic underflow), the
exceptional operand exponent value is set to $0000. This is the smallest exception
operand exponent value that can be produced by a normal underflow ($16001 +
$3FFF + $6000, truncated to 15 bits), while the largest underflow exponent value is
$5FFF ($1C000 + $3FFF + $6000, truncated to 15 bits). The catastrophic underflow ex-
ceptional operand exponent value of $0000 is produced any time the unbiased 17-bit
exponent of a calculated intermediate result has a value less than or equal to $16001.
Note that the trap handler should use only the FMOVEM instructions to read or write to
the floating-point data registers since FMOVEM cannot generate further exceptions or
change the condition codes.
NOTE
The IEEE standard defines two causes of an underflow:
1.
.
When a result is very small, the absolute value of the number is less than.
the minimum number that can be represented by a normalized number in
a specific format.
When loss of accuracy occurs while attempting to calculate a very small
number (a loss of accuracy also causes an inexact exception).
The IEEE standard specifies that if the underflow trap is disabled, an underflow should
only be signaled when both of these cases are satisfied (i.e., the result is too small to
represent with a given format, and there is a loss of accuracy during the calculation of the
final result). If the trap is enabled, the underflow should be signaled any time a tiny result
is produced, regardless of whether accuracy is lost in calculating it.
The FPCP UNFL bit in the AEXC byte of the FPSR implements the IEEE trap disabled
definition, since it is only set when a very small number is generated and accuracy has
been lost when calculating that number. The UNFL bit in the EXC byte implements the
IEEE trap enabled definition, since it is set anytime a tiny number is generated. Thus, if
the FPCP underflow trap is enabled, a trap occurs when very small size alone is detected
(as the IEEE standard specifies) to support the emulation of machines that underflow to
zero, rather than using the IEEE gradual underflow method (i.e., denormalized numbers).
If the underflow trap is disabled, the UNFL bit in the AEXC byte may be examined at the
end of a calculation to determine if any result produced during the operation required
representation as a denormalized number, and accuracy was lost when denormalizing and
rounding that result.
MC68881/MC68882 USER'S MANUAL
FREESCALE
6-13
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