6
Note that the trap handler should use only the FMOVEM instruction to read or write the
floating-point data registers, since FMOVEM cannot generate further exceptions or change
the condition codes.
NOTE
The IEEE standard specifies that inexactness should be signaled on overflow as
well as for rounding. The FPCP implements this via the INEX bit in the FPSR AEXC
byte. However, the standard also indicates that the inexact trap should be taken
if an overflow occurs with the overflow trap disabled and the inexact trap enabled.
Therefore, the FPCP takes the inexact trap if this combination of conditions occurs,
even though the INEX1 or INEX2 bits may not be set in the FPSR EXC byte. In
this case, INEX is set in the AEXC byte and OVFL is set in both the EXC and AEXC
bytes.
6.1.8 Inexact Result on Decimal Input
In a general sense, inexact result 1 (INEX1) is the condition that exists when a packed
decimal operand cannot be converted exactly to extended precision in the current rounding
mode. If this condition occurs, the INEX1 bit is set in the FPSR exception status byte, and
the result of the decimal-to-binary conversion is rounded to extended precision (regardless
of FPSR mode byte rounding precision) as shown in Figure 6-3. The FPCP provides two
inexact bits (INEX1 and INEX2) to help distinguish between inexact results generated by
decimal input conversions (INEX1) and other inexact results (INEX2).
Trap Disabled Results:
If the instruction is an FMOVE to a floating-point data register, the
rounded result is stored in the floating-point data register. If the instruction is not an FMOVE,
the rounded result is used in the calculation.
Trap Enabled Results:
The result is generated in the same manner as if traps were disabled,
except that a take exception primitive is returned when the MPU reads the response CIR
of the FPCP. Since the MC68881 does not allow multiple floating-point concurrency, the
exception is always reported as a pre-instruction exception when the next floating-point
instruction is attempted. The MC68882, however, may report an exception as a mid-
instruction exception on a subsequent floating-point instruction.
The address of the instruction that caused the inexact decimal conversion is available to
the trap handler in the FPIAR. The trap handler can determine the location of the decimal
string by examining the instruction, although the effective address of the string must be
recalculated (if possible) by the trap handler. When an FSAVE is executed by an inexact
trap handler, the value of the exceptional operand in the state frame is not defined (refer
to 6.4.2
State Frame).
An inexact exception differs from the other exceptions in this respect.
If the inexact conversion is the only exception that occurs during the execution of an
instruction, the value of the exceptional operand is invalid. If multiple exceptions occur
during an instruction, the exceptional operand value is related to a higher priority exception.
Note that the trap handler should use only the FMOVEM instruction to read or write the
floating-point data registers, since FMOVEM cannot generate further exceptions or change
the condition codes.
FREESCALE
6-18
MC68881/MC68882 USER'S MANUAL
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