Freescale Semiconductor MC68881 - Page 243

6.1.9 Multiple Exceptions
Dual and triple instruction exceptions may be generated by a single instruction in a few
cases. When multiple exceptions occur with traps enabled for more than one exception
class, only the highest priority exception trap is taken; the other enabled exceptions do
not cause a trap. The higher priority trap handler must check for multiple exceptions, The
priority of the traps is as follows:
BSUN Highest Priority
SNAN
OPERR
OVFL
UNFL
DZ
INEX2/INEXl Lowest Priority
The multiple instruction exceptions that can occur are:
SNAN and INEXl
OPERR and INEX2
OPERR and INEXl
OVFL and INEX2 and/or INEXl
UNFL and INEX2 and/or INEXl
INEX2 and INEXl
6.1.10 IEEE Exception and Trap Compatibility
The IEEE standard defines only five exceptions. The FPCP FPSR AEXC byte contains bits
representing these five exceptions, which are defined to function exactly as the standard
specifies the exceptions. However, it may be more useful to differentiate the IEEE required
exceptions into the eight exceptions represented in the FPSR EXC byte. Since the FPCP
uses the bits in the FPSR EXC byte and the FPCR ENABLE byte to determine when to trap,
there are seven possible instruction traps defined (INEX1 and INEX2 share one exception
vectorl instead of the five defined by the standard.
If it is necessary to write an application program that only supports the five IEEE specified
traps, the BSUN, SNAN, and OPERR exception vectors should be set to point to the same
handler routine. This allows the FPCP to support the invalid operation exception defined
in the IEEE standard, which is represented by the invalid operation (lOP) bit in the AEXC
byte.
To satisfy other requirements in the IEEE standard, the FPCP does the following:
1. A one is ORed into the AEXC byte lOP bit if the BSUN, SNAN, or OPERR bit is set in
the EXC byte.
2. A one is ORed into the AEXC byte UNFL bit only if both the UNFL and the INEX2 bits
of the EXC byte are set. However, per the IEEE standard, the underflow trap is based
only on the UNFL bit in the EXC byte,.
3. A one is ORed into the AEXC byte INEX bit if the INEX1, INEX2 or OVFL bit is set in
the EXC byte.
4. The IEEE standard requires that an inexact trap be taken if it is enabled, an overflow
occurs, and the overflow trap is disabled. Thus, if the OVFL bit is set in the EXC byte,
the OVFL bit is not set in the ENABLE byte, and the INEX2 bit is set in the ENABLE
byte, then the inexact trap is taken,
MC68881/MC68882 USER'S MANUAL
FREESCALE
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