6
The equations for items
1, 2, and 3
are:
AEXC(IOP) = AEXC(IOP)vEXC(BSUNvSNANvOPERR)
AEXC(UNFL) = AEXC(UNFL)vEXC(UNFLAINEX2)
AEXC(INEX) = AEXC(INEX)vEXC(INEXlvINEX2vOVFL)
The equation for item 4 (inexact trap taken) is:
Inexact Trap =
[[EXC(OVFL)vEXC(INEX2)]AENABLE(INEX2)]v[EXC(INEX1)AENABLE(INEX1)]
where:
"v'"
= logical OR
"'A"=
logical AND
6.1.11 Illegal Command Words
Illegal coprocessor commands are coprocessor command word bit patterns that are not
implemented by the FPCP. The FPCP reports illegal coprocessor commands as pre-instruc-
tion exceptions, using the F-line emulator vector number. The specific illegal command
word bit patterns are defined in 4.7 INSTRUCTION ENCODING DETAILS.
FPCP instructions consist of an operation word, a coprocessor command word (if any),
and extension words (if any). The MPU detects an illegal operation word and the FPCP
detects an illegal command word.
For the case where a coprocessor-detected instruction trap is pending when the MPU writes
an illegal coprocessor command to the FPCP command CIR, the coprocessor first reports
the pending instruction exception as a pre-instruction exception. Following exception proc-
essing of the instruction exception, the MPU resumes execution of the main program at
the beginning of the illegal coprocessor command, by writing to the command CIR again.
The illegal instruction exception is then reported by the FPCP.
6.1.12 Coprocessor-Detected Protocol Violation
All interprocessor communications in the coprocessor interface occur as standard M68000
bus cycles. A failure in this communication results in the FPCP reporting a mid-instruction
exception with the coprocessor protocol violation vector number. When a protocol violation
has been detected by the FPCP, the response CIR is encoded to the take mid-instruction
primitive and the next read of the response CIR by the main processor terminates the
dialog.
The MC68881 signals a protocol violation when unexpected accesses of the command,
condition, register select, or operand CIRs occur. Coprocessor detected protocol violations
occur when:
1. The MC68881 is expecting a write to the command or condition CIR, and instead an
access of the register select or operand CIR occurs.
2. The MC68881 is expecting a read of the register select or operand CIR, and instead
a write to the command, condition, or
operand
CIR
occurs.
3. The MC68881 is expecting a write to the operand CIR, and instead either a write to
the command orto the condition CIR or a read of the register select or of the operand
CIR occurs
FREESCALE
6-20
MC68881/MC68882 USER'S MANUAL
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