The MC68882 signals a protocol violation when unexpected accesses of the command,
condition, register select, operand, or instruction address CIRs occur. For the MC68882,
coprocessor-detected protocol violations occur when:
1. The MC68882 is expecting a write to the command or condition CIR, but a read or
write operation to the register select CIR or to the operand CIR or a write operation
to the instruction address CIR occurs instead.
2. The MC68882 is expecting a read of the register select CIR or of the operand CIR, but
a write operation to the command CIR, the condition CIR, the operand CIR, the in-
struction address CIR, or the register select CIRoccurs instead.
3. The MC68882 is expecting a write operation to the operand CIR, but a write operation
to the command CIR or to the condition CIR or a read of the register select CIR, the
operand CIR, or instruction address CIR occurs instead.
4. The MC68882 is expecting a write operation to the instruction address CIR, but a write
operation to the command CIR, the condition CIR, the operand CIR, or the register
select CIR or a read of the operand CIR or the register select CIR occurs instead.
For these violations, the FPCP maps the 16-bit register select CIR onto the upper word of
the 32-bit operand register. Thus, inconsistent data is read from the operand CIR, and write
cycles cannot store the correct value. Of course, this is of no consequence since the protocol
violation invalidates any operation being attempted by the FPCP or the main processor.
During normal operation, the FPCP synchronizes interprocessor communication by delay-
ing the assertion of DSACKx, if necessary. However, upon detection of a protocol violation,
the MC68881 always terminates the access by immediately asserting DSACKx.
Note that in certain cases resulting from serious system programming errors, an unre-
coverable protocol violation may occur when using the MC68882. This particular case of
the protocol violation occurs during the coprocessor interface dialog for the FMOVE and
FMOVEM instructions if a read of the operand CIR occurs before the evaluate <ea> and
transfer data (DR=l) or the transfer multiple coprocessor registers (DR= 1) primitive is
issued. In this case, the protocol violation is not reported via the take mid-instruction
primitive as is the normal case. Instead, the MC68882 ignores the access completely, and
it is the responsibility of the system watchdog timer to abort the access to the operand
CIR by asserting the bus error signal to the main processor. The MC68020 and MC68030
cannot cause this protocol violation to occur except through misuse of the MOVES instruc-
tion.
Spurious coprocessor-detected protocol violations may also be caused by hardware timing
design errors. When using an MC68020 or MC68030, a common oversight is to use a
buffered address strobe (AS) to the FPCP while not buffering the lower address lines
supplied to the FPCP. If the A-S buffer delay used is long enough, it is possible to violate
FPCP specification #7. This problem is usually indicated by protocol violations during
FMOVEM instructions.
A protocol violation cannot occur as a result of an access to the reserved register locations,
a read of a write-only register, or a write to a read-only register (a read of a reserved or
write-only register always returns a value of all ones). One exception to this rule is that a
write access to the register select CIR causes a protocol violation. Reads of the save or
response CIR are always valid as are writes to the restore or control CIR.
MC68881/MC68882 USER'S MANUAL FREESCALE
6-21
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