6
While the MC68881 can request that the MPU write the instruction address CIR (by setting
the PC bit in a primitive response), accesses of this register are neither expected or un-
expected. Thus, when the MC68881 is utilized as a peripheral processor where no con-
current instruction execution occurs, requests to transfer the PC may be ignored without
incurring a protocol violation. When the instruction address CIR is written by the main
processor, the MC68881 updates the FPIAR with the written value without regard to "correct"
protocol.
Since the MC68882 provides concurrent execution of multiple floating-point instructions,
it requires program counter values to be transferred when requested to guarantee a valid
FPIAR for a concurrently-executed instruction which reports an exception. Whenever the
MC68882 requests the PC value, it reports a protocol violation if the main processor does
not transfer the PC value by writing the instruction address CIR.
A protocol violation is the highest priority coprocessor-detected exception. It is also con-
sidered to be a fatal exception, since the MPU acknowledgment of the protocol violation
exception clears any pending FPCP instruction exceptions and aborts any instruction in
progress.
NOTE
To distinguish between a protocol violation detected by the MPU or the FPCP, an
exception handler can read the response CIR and evaluate the returned primitive.
If the protocol
violation
is detected by the FPCP due to an unexpected access, the
operation being executed previously is aborted, and the FPCP assumes the idle
state when theexception acknowledge is received. Therefore, the primitive read
from the response CIR is null (CA=0). If the protocol violation is detected by the
MPU due to an illegal primitive, the FPCP response CIR contains that primitive
when the exception handler reads it. (Since the FPCP cannot internally generate
an illegal primitive, an MPU detected protocol violation indicates a hardware
failure.)
To read the response CIR in a hardware independent manner, the trap handler should use
the move alternate address space (MOVES) instruction. For example, the following instruc-
tion sequence reads the response CIR of the coprocessor with CPID= 1 into an MPU
data
register:
MOVE.B #7,D0 Prepare the SFC register
MOVEC D0,SFC for a CPU space cycle...
MOVES.W $00022000,D0 Execute a "coprocessor" cycle.
6.1.13 Recovery from Exceptions
When a coprocessor-detected exception occurs, enough information is made available to
the trap handler to perform the necessary corrective action and then resume execution of
the program that caused the exception. Of course, in some instances, it may not be valid
to resume execution of the program; recovery is not possible for protocol violations. The
information available to an exception handler is described in the previous sections, and
the following paragraphs describe the methods used to resume execution of e program
after an exception is appropriately handled.
In all cases, the stack frame generated by the MPU in response to a coprocessor-detected
exception contains a program counter value that points to the instruction to be executed
FREESCALE
6-22
MC68881/MC68882 USER'S MANUAL
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