6
the program that caused the exception. For the MC68882, all exception handlers must
begin with an FSAVE instruction, even when they do not contain any floating-point in-
structions. The FPIAR value must be saved before any instruction other than an FMOVEM
is executed, so that the address of the instruction that caused the exception is not lost.
When the exception handler completes the error recovery and is prepared to return to the
suspended program, an FRESTORE is executed as the last FPCP instruction; this restores
the previous context of the program that caused the exception. Refer to 5.2.2 Exception
Handler Code
for other requirements of the MC68882 exception handler.
6.2 MAIN PROCESSOR DETECTED EXCEPTIONS
The following paragraphs describe exceptions that are detected by the MPU during FPCP
instruction execution. Refer to the main processor user's manual for additional information
on these exceptions, and the pre- and mid-instruction exception main processor stack
frames.
6.2.1 Trap on Coprocessor Condition Instruction
The FPCP trap on condition instruction is initiated when the MPU writes a conditional
predicate to the FPCP for evaluation and reads a true/false result in the FPCP response
primitive. If the FPCP indicates that the condition is true, the MPU takes a post-instruction
exception using the TRAPV/TRAPcc vector number.
The stack frame generated by the MPU in response to this exception contains two uointer
values:
1. A pointer to the FTRAPcc instruction that caused the exception
2. A pointer to the instruction that follows the FTRAPcc (the pointer to which the pro-
cessor returns if an RTE instruction is executed)
6.2,2 Illegal Instructions
The FPCP instructions consist of an operation word, a coprocessor command word (if any),
and extension words (if any). The MPU detects illegal operation words, and the FPCP detects
illegal command words. When the MPU detects an illegal operation word for a coprocessor
instruction, it takes a pre-instruction exception using the F-line emulator vector number.
Refer to 4.7 INSTRUCTION ENCODING DETAILS for specific bit pat-terns that are illegal
coprocessor operation words.
In addition to detecting an illegal operation word, the MPU can detect an illegal instruction
even though the operation word is valid. This occurs when the addressing mode of the
instruction is not valid. When the FPCP returns a primitive response to the MPU that
requests a data transfer to or from the effective address, the FPCP either implicitly or
explicitly indicates the valid addressing modes for an instruction. Thus, the MPU can
determine that properly formed FPCP operation words and primitive responses are invalid
if they specify operations that are illegal, such as writing to a nonalterable effective address.
When the MPU detects an invalid instruction in this manner, it terminates the FPCP exe-
cution of the instruction by writing an abort to the control CIR. (The MC68882 only aborts
FREESCALE
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MC68881/MC68882 USER'S MANUAL
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