the instruction with the invalid effective address without disturbing concurrently-executed
instructions. The MPU then takes a pre-instruction exception using the F-line emulator
vector number. Termination of the FPCP instruction execution in this manner does not
alter any visible processor or coprocessor registers or status (such as pending coprocessor
exceptions). Use of the F-line emulator trap allows the operating system to emulate any
extensions to the FPCP that are not supported by a specific processor.
6.2.3 Main-Processor-Detected Protocol Violations
If the MPU reads an FPCP response primitive that it interprets as an illegal primitive, it
does not terminate the FPCP execution of the instruction by writing to the coprocessor
interface control register. Instead, the MPU takes a mid-instruction exception using the
coprocessor protocol violation vector number.
Since the FPCP never issues an illegal response primitive, this feature of the MPU serves
to detect a failure of interprocessor communications. If a protocol violation is taken on an
FPCP instruction, whether detected by the FPCP or the MPU, a system failure may be
assumed. Refer to 6.1.12
Coprocessor-Detected Protocol
Violation for an example of how
an exception handler can determine the cause of a protocol violation.
6.2,4 Trace Exceptions
To aid in program development, the MPU includes a facility to allow instruction-by-instruc-
tion tracing. In the single-step trace mode, after each instruction is executed, the MPU
takes a post-instruction exception using the trace vector number. This allows a debugging
program in the trace exception handler to monitor the execution of a program under test.
Refer to the main processor user's manual for a complete description of the trace mode.
Many FPCP instructions can operate concurrently with MPU instructions, and defer the
reporting of coprocessor detected instruction exceptions until the next FPCP instruction is
dispatched by the MPU. This provides a sequential instruction execution model even though
concurrent instruction execution may occur. To guarantee that pending exceptions are
always reported at the same point in an instruction sequence, regardless of whether tracing
is enabled, the FPCP always releases the MPU at the end of an instruction that allows
concurrency before reporting the exception. This sequence is important, because the MPU
(when in the trace mode) waits for an instruction to complete before proceeding.
To provide consistent reporting of exceptions, the FPCP always returns the null (CA=0,
PF = 1) primitive when it completes execution of an instruction that allows concurrency,
and then reports a pending exception only after a write to the command or condition CIR.
The synchronization of the two devices in the trace mode is accomplished through the PF
bit in the null primitive (see 7.1 CHIP-SELECT DECODE). When the trace mode is enabled,
the MPU repeatedly reads the response CIR to determine when the FPCP completes in-
struction execution. If the null (CA=0, IA= 1, PF=0) primitive is read, then the MPU checks
for pending interrupts, and if none are pending, reads the response CIR again. This process
continues until the MPU receives a null (CA=0, PF= 1) primitive from the FPCP, at which
time it performs the trace exception processing.
MC66661/MC66662 USER'S MANUAL FREESCALE
6-25
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