7
handlers in the most efficient manner.) When the coprocessor is an MC68882, the main
processor must transfer the program counter value. The MC68882 issues a protocol vio-
lation when the main processor fails to transfer the program counter value. The MPU
always transfers the PC when needed.
For the MC68881, accesses to the instruction address CIR are neither expected nor unex-
pected at any point in an instruction dialog; thus, an access to this CIR location never
causes a protocol violation. A write to the instruction address CIR updates the FPIAR register
in the MC68881 programming model; a read always returns all ones.
Internally, the MC68882 has three instruction address registers. One register is associated
with each of the stages of the MC68882 pipeline (BIU, CU, and APU). The instruction address
register associated with the arithmetic processing unit (APU) isthe floating-point instruction
address register (FPIAR). Since only the APU can report an exception, the FPIAR always
points to the instruction that causes the exception whenever an exception occurs. When
the instruction address CIR is written (whenever the program counter value is passed), the
program counter value is also written to the instruction address register associated with
the bus interface unit (BIU) stage of the pipeline. The MC68882 interprets this program
counter value as the address of the instruction currently in the BIU. The instruction and
its address are moved up the pipeline until the instruction reaches the APU stage of the
pipeline. If that instruction causes an exception, its address is in the FPIAR (since the FPIAR
is the instruction address register for the APU). This implementation is necessary to ensure
that an exception handler can point to the correct instruction, the one that causes the
exception. However, this implementation requires that the instruction address CIR be writ-
ten whenever the MC68882 requests it. The MC68882 issues a protocol violation whenever
the main processor fails to supply the requested program counter value. A read of the
instruction address CIR always returns all ones.
7.2.11 Operand Address CIR ($1C}
This 32-bit
read~write
register is used by the main processor to transfer an operand address
in response to the evaluate and transfer effective address or take address and transfer data
primitives. Since the FPCP does not utilize either of these primitives, this CIR is not required
for operation and is not implemented. An access to this CIR location does not cause a
protocol violation; read cycles always return all ones, and the data is ignored during write
accesses,
7.3 INTERPROCESSOR TRANSFERS
All interprocessor transfers are initiated by the MPU. During the processing of an FPCP
instruction, the MPU transfers instruction information and data to the FPCP using standard
M68000 write bus cycles. The MPU also receives data, requests for service, and status
information from the FPCP using standard M68000 read bus cycles. A detailed description
of the electrical characteristics of the FPCP bus interface is contained in SECTION 10
BUS
OPERATION and SECTION 12 ELECTRICAL SPECIFICATIONS.
7.4 COPROCESSOR INSTRUCTIONS
FPCP instructions are from one to eight words in length. The first word of the instruction
is called the operation word, and the second word of the instruction is called the copro-
cessor command word. Additional words specify the operands and are either extensions
FREESCALE
7-8
MC68881/MC68882 USER'S MANUAL
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