7
registers primitive should not be ignored. The FPCP sets the CA bit in these primitives to
assure correct operation regardless of the frequency relationship between the FPCP clock
and the main processor clock. By requiring the main processor to perform a final read of
the response CIR (which is a cycle that is synchronous with the FPCP CLK signal) after the
last operand CIR access and before continuing with the next instruction, the FPCP assures
that the operand transfer is completed internally before the main processor can initiate
the next instruction by writing the command or condition CIRs. This sequence assures that
spurious protocol violations (detected by the FPCP) do not occur in systems where the
main processor clock frequency is much faster than the MC68881 clock frequency.
During the instruction dialogs for external-to-register (opclass 010 and register-to-external
(opclass 011 )) instructions, the MC68882 in some cases issues the evaluate effective address
and transfer data primitive with CA=0 instead of CA= 1. In these cases, the main processor
need not read the response CIR after the coprocessor has transferred the operands for that
instruction. This provides more potential instruction overlap with the next coprocessor
instruction. Normally, a second coprocessor instruction causes the main processor to write
to the command or condition CIR and then to read from the response CIR. If the read from
the response CIR of the
second
instruction occurs earlier than three clocks
after
the com-
pletion of the last operand transfer of the previous instruction, spurious protocol
violations
may occur. In a worst-case situation, the main processor uses these three clocks in writing
to the command CIR. However, if the main processor has a higher clock frequency than
the MC68882, it is possible that the write to the command CIR can take less than three
MC68882 clocks. The design of the MC68882 allows the MPU clock frequency to be as
much as 1.5 times the MC68882 clock frequency. For main processors other than the
MC68020 or MC68030, the system designer must ensure that the main processor does not
read the response CIR during the initiation of an instruction less than three MC68882 clocks
after the last operand transfer of the previous instruction.
7.5.1.1 REGISTER-TO-REGISTER (OPCLASS 000). This dialog is utilized for all of the arith-
metic and move instructions that use floating-point data registers for both the source and
destination operands and for the FMOVECR instruction. Since the FPCP contains both
operands when such an instruction is initiated, no external data references are required
before the calculation can be performed. Thus, after the MPU has written the command
word to the FPCP, it is released to execute the next instruction. If any arithmetic exceptions
are enabled, the FPCP requests the transfer of the program counter. This request can be
ignored by a main processor using an MC68881, but the MC68882 issues a protocol violation
if the main processor ignores this request. The program counter write cycle does not affect
instruction execution time (since it occurs concurrently with the FPCP instruction execution).
The FPCP dialog for this instruction type is shown in Figure 7-17. Also shown in this figure
is the key for all of the dialog figures presented in subsequent paragraphs.
7.5.1.2 EXTERNAL-TO-REGISTER (OPCLASS 010). This dialog is utilized for all of the
arithmetic and move instructions that reference memory or a main processor register for
the source operand. Since the FPCP does not contain both operands when such an instruc-
tion is initiated, external data references are required before the calculation can be per-
formed. The FPCP requests the fetch of the required external operand with the first primitive
of the dialog. The second primitive of the dialog is then used to release the main processor
to execute the next instruction (once the operand transfer is completed). Note that the read
of the first primitive causes the response CIR encoding to be changed to the null primitive,
FREESCALE
7-22
MC68881/MC68882 USER'S MANUAL
To Next Page
Loading...