CIR. In this response, the BIU encodes requests for any additional service required of the
MPU on behalf of the FPCP. For example, the response may request that the MPU fetch
an operand from the evaluated effective address and transfer the operand to the operand
CIR. Once the MPU fulfills the coprocessor request(s), the MPU is free to fetch and execute
subsequent instructions.
A key concern in a coprocessor interface that allows concurrent instruction execution is
synchronization during main processor and coprocessor communication. If a subsequent
instruction is written to the command CIR before the APU has completed execution of the
previous instruction (in the case of the MC68881) or before the CU has passed its results
to the APU (in the case of the MC68882), the response instructs the MPU to wait. Thus,
the choice of concurrent or nonconcurrent instruction execution is determined on an in-
struction-by-instruction basis by the coprocessor.
The only difference between a coprocessor bus transfer and any other bus transfer by the
MPU is that the function code issued by the MPU specifies the CPU address space during
the cycle (the function codes are generated by the M68000 Family processors to identify
one of eight separate address spaces). Thus, the memory-mapped coprocessor interface
registers do not infringe upon instruction or data address spaces. The MPU places a co-
processor ID field from the coprocessor instruction words onto three of the upper address
lines during coprocessor accesses. This ID, along with the CPU address space function
code, is decoded to select one of eight possible coprocessors in the system.
Since the coprocessor interface protocol consists solely of bus transfers, the protocol is
easily emulated by software when the FPCP is used as a peripheral with any processor
capable of memory-mapped I/O over an M68000-style bus. When used as a peripheral
processor with the 8-bit MC68008 or either the 16-bit MC68000 or MC68010, all FPCP
instructions are trapped by the main processor to an exception handler at execution time.
Trapping the instructions enables the software emulation of the coprocessor interface
protocol to be totally transparent to the user. The FPCP can provide a performance option
for MC68000-based designs by changing the main processor to an MC68020 or MC68030.
The software migrates without change to the next generation equipment using the MPU.
Since the bus is asynchronous, the FPCP need not run at the same clock speed as the main
processor. Total system performance can therefore be customized. For a given CPU per-
formance requirement, the floating-point performance can be selected to meet particular
price/performance specifications, running the FPCP at slower (or faster) clock speeds than
the CPU clock.
1.2.2 Coprocessor Interface
The M68000 Family coprocessor interface is an integral part of the FPCP and MPU designs.
The interface partitions MPU and coprocessor operations so that the MPU does not have
to completely decode coprocessor instructions, and the FPCP does not haveto duplicate
main processor functions (such as effective address evaluation).
This partitioning provides an orthogonal extension of the instruction set by permitting
FPCP instructions to utilize all MPU addressing modes and to generate execution time
exception traps. Thus, from the programmer's view, the MPU and coprocessor appear to
be integrated onto a single chip. While the execution of the great majority of FPCP instruc-
tions can be overlapped with the execution of MPU instructions, concurrency is completely
MC68881/MC68882 USER'S MANUAL
FREESCALE
1-9
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