transparent to the programmer. The MPU single-step and program flow (trace) modes are
fully supported by the FPCP and the M68000 Family coprocessor interface.
While the M68000 Family coprocessor interface permits coprocessors to be bus masters,
the FPCP never functions
as
one. The FPCP requests that the MPU fetch all operands and
store all results. In this manner, the MPU 32-bit data bus provides high-speed transfer of
floating-point operands and results while reducing the pin count of the FPCP.
Since the coprocessor interface consists solely of bus cycles (to and from the CPU space)
and the FPCP never functions as a bus master, the coprocessor can be placed on either
the logical or physical side of the system memory management unit (MMU) in an MC68020
system. Since the MMU of the MC68030 is on-chip, the FPCP is always on the physical
side of the MMU in an MC68030 system.
The virtual machine architecture of the MPU is supported bythe coprocessor interface and
the FPCP with the FSAVE and FRESTORE instructions. If the MPU detects a page fault and/
or a task timeout, the MPU can force the FPCP to stop whatever operation is in progress
at any time and save the FPCP internal state in memory. During the execution of a floating-
point instruction, the FPCP can stop at predetermined points as well as at the completion
of the instruction.
The size of the saved internal state of the FPCP is dependent upon the state of the APU at
the time that the FSAVE is executed. If the MPU is in the reset state when the FSAVE
instruction is initiated, only one word of state is transferred to memory. The stored word
may be examined by the operating system to determine that the coprocessor programmer's
model is empty. If the APU is in the idle state when the FSAVE instruction is decoded, only
a few words of internal state are transferred to memory. If the APU is in the middle of
executing an instruction, it may be necessary tO save the entire internal state of the machine.
Instructions that can complete execution in less time than it would take to save the larger
state in mid-instruction are automatically allowed to complete execution and then save
the idle state. Thus, the size of the saved internal state is kept to a minimum. The ability
to utilize several internal state sizes greatly reduces the average context switching time.
The FRESTORE instruction permits reloading an internal state saved earlier and continues
any previously suspended operation. Restoring the reset internal state re-establishes de-
fault register values, a function identical to the FPCP hardware reset.
1.3 OPERAND DATA FORMATS
The FPCP supports the following data formats:
Byte Integer (B)
Word Integer (W)
Long Word Integer (L)
Single Precision Real (S)
Double Precision Real (D)
Extended Precision Real (X)
Packed Decimal String Real (P)
The capital letters within the parentheses denote suffixes added to mnemonics of the
assembly language instructions to specify the data format to be used.
FREESCALE
1-10
MC68881/MC68882 USER'S MANUAL
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