8
• When the main processor initiates a command to the FPCP, any previous floating-
point instruction has been completed and the FPCP is in the idle state.
• All operands in memory, as well as the system stack,
are
long word aligned.
• A 32-bit data bus is used for communications between the MC68020 and both the
FPCP and the system memory.
• All memory accesses occur with no wait states (i.e., three clock cycle reads and writes).
• All coprocessor accesses, except those to the response and save CIRs, occur with no
wait states. Accesses to the response and save CIRs require two wait cycles (five clock
reads).
Note that the clock signal relationship between the MC68020~MC68030 (MPU) and the FPCP
assumed for these discussions is not a system requirement, but merely a simplification
that allows easy measurement of instruction times. However, the ratio of MPU clock fre-
quency to FPCP clock frequency can be any reasonable value. In general, the clock frequency
of the FPCP affects absolute instruction timing more than that of the MPU, since floating-
point operations are usually computation intensive. However, the clock frequency rela-
tionship of the MPU and FPCP can affect the execution time of an instruction due to the
time needed to transfer operands of various sizes and due to actual activity of the two
devices. The magnitude of the dependency of execution times on the clock frequency of
the MPU varies with instruction types, since some instructions spend a relatively small
amount of their overall execution time in communication with the main processor; whereas,
other instructions spend almost all of their execution time in communication with the main
processor.
With this set of assumptions as a starting point, several factors must be defined that
contribute to the overall execution time for a given instruction. Some of these factors are
common to all instructions, while others are only applicable to certain instructions or data
types. Particularly, the execution times for the conditional and system control instructions
are not widely variable, but the execution time for an arithmetic or data movement in-
struction is heavily affected by data values and exception checking. In order to better
understand how these factors are combined to calculate the execution time for an arithmetic
or move-to-floating-point register instruction, it is helpful to divide coprocessor instruction
execution into the following steps:
1. Receive the command word from the host processor, decode it, and return the first
service request primitive.
2. Receive the main processor program counter, if required.
3. Receive an external operand, if required.
4. Convert the operand to the internal extended format.
5, Perform the algorithm specified by the command word on the operand(s).
6. Round the result to the correct precision, check the result of the computation for
conditions such as overflow, then store the result into a floating-point data register.
The first three of these steps require approximately the same amount of time for any
instruction, but the last three steps can require widely varying amounts of time even when
comparing the execution time for a given instruction with different data inputs. For pur-
poses of this discussion, the first three steps are referred to as the instruction start-up
phase, the fourth step as the conversion phase, the fifth step as the calculation phase, and
FREESCALE
8-2
MC68881/MC68882 USER'S MANUAL
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