The MC68882, however, can obtain the operand of a subsequent floating-point instruction
and convert the operand to internal format during the tail of the previous instruction. This
portion of the instruction is defined as the head of the MC68882 instruction. It is the portion
of the instruction that begins when the instruction is initiated by the MPU, and ends when
the present coprocessor instruction can no longer operate under the tail of a previous
instruction. The actual values of head and tail that apply to the MC68882 floating-point
instructions are shown in Table 8-3. The tails of MC68882 floating-point instructions can
execute concurrently with MPU instructions as well as with other MC68882 instructions.
The head times for the MC68882 instructions indicate the degree of concurrency that is
allowed.
Each floating-point instruction of the MC68882 is either fully concurrent, partially concur-
rent, or nonconcurrent. Instructions for which the head time equals the total execution
time are fully concurrent. Those for which head and tail values are shown are partially
concurrent. The instructions that have zero head values are noncurrent.
Concurrent execution of floating-point instructions in the MC68882 can significantly im-
prove coprocessor performance. Refer to 5.1.2 Optimization of Code for the MC68882 for
more information on the effects of concurrency on the performance of programs.
8.3 INTERRUPT LATENCY TIMES
In real-time systems, a very important factor pertaining to overall system performance is
the response time required for a processor to handle an interrupt. In the M68000 Family
of processors, interrupts are allowed to be asserted to the processor asynchronously, and
they are handled on the next instruction boundary~ While the average interrupt latency for
the MPU is quite short, the maximum latency is often of critical importance since real-time
interrupts cannot require servicing in less than the maximum interrupt latency. The max-
imum interrupt latency for the MPU is approximately 250 clock cycles (for the MOVEM.L
([d32,An],Xn,d32), D0-D7/A0-A7 instruction where the fast data fetch is aborted with a bus
error; refer to the MC68020 user's manual or the MC68030 user's manaul for more detailed
information), but some FPCP instructions may take two or three times that long to execute
with typical operand types, combinations and values.
It may be unacceptable in a real-time system to have a worst-case interrupt latency time
as large as 600 or more clock cycles (the length of some long floating-point instructions).
Therefore, the FPCP allows interrupts to be processed in the middle of the execution of a
floating-point instruction, whenever possible, to reduce the latency time. The FPCP
does
this in four ways:
1. By returning the null (CA--0, IA=I, PF=0) primitive when it enters the calculated
phase of an instruction that allows concurrency. If the MPU is not in the trace mode,
it is then free to fetch the next instruction and process any pending interrupts at the
instruction boundary. If the MPU is in the trace mode, it waits for the FPCP to complete
execution and return the null (CA--0, PF= 1) primitive before continuing with the next
instruction, but it services pending interrupts while it is waiting.
2. By returning the null (CA= 1, IA= 1) primitive when the main processor attempts to
initiate a
floating-point
instruction while the FPCP is unable to begin another operation,
thus allowing the MPU to service interrupts while waiting for the coprocessor to start
execution
of the new instruction.
MC68881/MC68882 USER'S MANUAL FREESCALE
8-5
To Next Page
Loading...