cycles may require as many as six or seven clock cycles. Two separate mechanisms de-
termine whether additional clock cycles are required for this type of a bus cycle:
1. The relationship between the assertion of AS, DS, or CS and the rising edge of the
FPCP clock signal
2. The relationship between the assertion of DSACKx by the FPCP and the falling edge
of the MPU clock signal
As previously described, DSACKx is triggered to assert one and one-half clock cycles after
AS, DS, and C--S are sampled as asserted; thus, the best-case timing occurs when all three
of these signals are asserted as early in the bus cycle as possible. Since the MPU triggers
the assertion of AS and DS with the falling edge of the CLK signal (which is assumed to
be the same for both devices) and the FPCP samples those signals, along with CS, on the
rising edge of the CLK signal, the best-case cycle timing occurs only if AS, DS, and CS are
all asserted to provide the required setup time to the next rising edge of the clock. Thus,
the maximum assertion and propagation delays for these signals must be less than the
clock pulse width low in order to guarantee the best-case bus cycle timing. Although the
maximum specifications for the assertion, by the MPU, of AS or DS from the falling edge
of the clock do not guarantee the best-case timing for operation at 16.67 MHz under worst-
case system environments, the best-case timing normally occurs under typical system
conditions. In order to assure the possibility that the best-case timing occurs, system
designers should utilize the C~ generation methods described in 10.3 CHIP SELECT TIMING
to prevent propagation delays of the CS logic from lengthening the bus cycle by one clock.
In the same manner as just described (where the FPCP misses the assertion of AS, DS, or
C-S), one clock cycle may be added to the bus cycle timing if the MPU misses the assertion
of DSACKx by the FPCP. The assertion of DSACKx by the FPCP is triggered by the falling
edge of the clock, and the propagation delay for this assertion can be quite long (slightly
longer than one 16.67 MHz clock cycle under worst-case system conditions). Since the
MPU samples DSACKx on the falling edge of the clock, the assertion of DSACKx triggered
by a given falling clock edge may not be completed ahead of the setup time to the next
falling clock edge. There is very little that a system designer can do to assure that the
DSACKx assertion is recognized on the first falling clock edge after it is triggered, since
the propagation delay is dependent on individual device characteristics as well as system
conditions such as temperature and power supply levels.
Due to the nature of the two mechanisms just described, it is possible that for an individual
system the bus cycle timing for synchronous read cycles may be different under varying
system conditions. For example, when a system is first turned on (and thus the devices
are at room temperature) it is quite likely that synchronous read cycles require five clock
cycles as shown in Figure 10-6. As the temperature increases to the normal operating
range, the synchronous read cycle timing may change to six clock cycles. If the temperature__
.rise affects both of the synchronization mechanisms enough (particularly if_.the CS gen-
eration logic causes the assertion of C--S to follow the assertion of AS and/or DS), the timing
for these operations may increase to seven clock cycles or even vary on a cycle-by-cycle
basis between six and seven clock cycles. Some other factors that may affect the timing
for synchronous reads cycles are the power supply levels for the FPCP and MPU, the
individual device characteristics (due to manufacturing variances), and the capacitive load-
ing of the control signals.
It should be noted that the timing variances for synchronous read cycles do not affect the
overall performance of a system significantly. Specifically, one or two additional clock
MC68881/MC68882 USER'S MANUAL FREESCALE
10-11
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