--C--
Interface, 1-2, 1-9, 7-1
Overhead, 8-6
Overhead Timing, 8-8, 8-9
Protocol Restrictions, 10-15
Register, 1-6, 7-2, 7-3, 9-2, 10-1
Response Primitive, 7-10
Systems Programming, 5-10
Coprocessor-Detected
Exceptions, 6-2
Protocol Violation Exception, 6-20
Cp-ID, 7-9
C_PPU Space Types, 7-2
CS Signal, 7-3, 9-3, 10-6, 10-9, 10-11, 10-12
--I)--
D Format, 3-11
Data Bus, 7-3, 9-2, 10-1, 10-3-10-5, 11-2, 11-3
Bit Assignments, 10-2
Operand Alignment, 10-2
Size, 9-2
Data Formats, 1-10, 3-1
Data Movement Instructions, 4-2
Data Strobe Signal, 9-3, 10-6, 10-9-10-13
Data Transfer and Size Acknowledge Signals, 1-6,
6-21, 7-2, 7-3, 9-3, 10-2-10-5, 10-6,
10-9-10-11, 10-13, 11-2, 11-3
Data Types, 3-3, 3-13
Summary, 3-6
DC Electrical Characteristics, 12-2
Decimal Conversion Accuracy, 4-8
Decode, Chip Select, 7-1, 7-2, 11-3
Decoupling, VCC, 9-5
Definitions,
Conditional Test, 4-8
Format Word, 6-36
Denormalized Numbers, 3.4
Description, General, 1-1
Descriptions, Instruction, 4-18-4-124
Destination Format Field Encoding, 4-130
Destination Register Field, 4-139
Detection, Coprocessor, 5-15
Diagrams, Timing, Foldout
Dialog,
Conditional Instruction, 7-28
External-to-Register Instruction, 7-22
MC68882, 7-24
F-Line Emulator Exception, 7-39
Format Exception,
FRESTORE Instruction, 7-40
FSAVE Instruction, 7-39
FSAVE Instruction, 7-28
Mid-Instruction Interrupt, 7-35, 7-38
Move Control Registers Instruction, 7-26
Move Multiple FPn Registers Instruction, 7-27
OPCLASS 000 Instruction, 7-22
OPCLASS 010 Instruction, 7-22, 7-23
MC68882, 7-24
OPCLASS 011 Instruction, 7-24, 7-25
MC68882, 7-26
OPCLASS 100 Instruction, 7-26, 7-27
OPCLASS 101 Instruction, 7-26, 7-27
OPCLASS 110 Instruction, 7-27, 7-28
OPCLASS 111 Instruction, 7-27, 7-28
Register-to-External Instruction, 7-22, 7-23
MC68882, 7-26
Register-to-Register Instruction, 7-22
RESTORE Instruction, 7-30
Take BSUN Exception, 7-38
Take Mid-Instruction Exception, 7-32
MC68881, 7-34
MC68882, 7-34
Take Pre-lnstruction Exception, 7-31
MC68882, 7-33, 7-34
Dialogs,
Context Switch Instruction, 7-28
Exception Processing, 7-31
General Type Instruction, 7-21
Instruction, 7-19
Dimensions, Package, 13-3
Divide-by-Zero Exception, 6-14
Double Precision Format, 3-11
DR Bit, 7-10
DS Signal, 9-3, 10-6, 10-10-10-14
DSACK0 Signal, 1-4, 6-21, 7-3, 9-3,
10-2-10-4, 10-6, 10-10, 10-11, 10-13, 11-2,
11-3, 11.4
DSACK1 Signal, 1-5, 6-21, 7-3, 9-3,
10-2-10-4, 10-6, 10-10, 10-11, 10-13, 11-2,
11-3, 11-4
Dual Monadic Operation Instruction Format, 4-4
Dyadic Operation
Calculation Times, 8-30-8-33
Instruction, 1-14, 4-2, 4-3, 5-6
Format, 4-2
DZ Exception, 6-14
D0-D31 Signals, 7-3, 9-3, 10-1-10-5, 11-2-11-4
mE--
Early Chip Select Logic Example, 10-8
Effective Address
Calculation Timing, 8-11
Field, 4-138
Encoding, 4-140
Electrical Characteristics,
AC
Clock Input, 12-3
Read and Write Cycles, 12-4
DC, 12-2
Electrical Specifications, 12-1
ENABLE Byte, 6-4, 6-19, 6-34, 6-35
Encoding,
Conditional Instruction, 4-133
Conditional Predicate Field, 4-140
Destination Format Field, 4-130
Effective Address Field, 4-139
Extension Field, 4-128, 4-131
Move FPcr, 4-132
Move Multiple FPn, 4-134
Register Field, 4-127
Source Format Field, 4-129
MC68881/MC68882 USER'S MANUAL FREESCALE
INDEX-3
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