Initial Phase, 6-38
Input Operand Conversion Times, 8-28, 9-29
Instruction
Concurrency, 5-1
Conditional, 1-14, 5-7
Coprocessor, 7-8
Description
Conventions, 4-1
Format, 4-14
Notations, 4-17
Descriptions, 4-18-4-124
Dialogs, 7-19
Dyadic Operation, 1-14, 4-2, 4-3, 5-6
Execution,
Concurrent, 8-4
Timing Chart, 8-5
Format Summary, 4-141--4-150
FSGLDIV, 4-17
FSGLMUL, 4-17
Miscellaneous, 1-15
Monadic Operation, 1-14, 4-3, 5-5
Move, 1-13
Operation Word, 7-9
Overlap
Example, MC68881, 8-22, 8-23
Times, MC68881, 8-40
protocol, 7-9
• Sequence,
Context Restore, 6-40
Context Save, 6-40
Set, 1-12
Start-Up Times, 8-25
Termination Times, 8-38
Instruction Address CIR, 6-20-6-22, 7-7
Instructions,
Constant-to-Register, 4-129
Data Movement, 4-2
External-to-Register, 4-127
Fully-Concurrent, 5-6
Minimum Concurrency, 5-5
Move Control Registers, 4-130
Move Multiple FPn Registers, 1-13, 4-130
Partially-Concurrent, 5-6
Program Control, 4-4
Register-to-Register, 4-127
System Control, 4-5
Integer
Computations, Concurrent, 5-1
Formats, 1-11, 3-1
Inter-Cycle Timing Restrictions, 10-14
Interface, Coprocessor, 1-2, 1-9, 7-1
Intermediate Result Format, 6-16
Internal Format, 3-7
Interprocessor Transfers, 7-8
Interrupt
Exception, 6-26
Latency, 8-5
Processing, 5-13
Task Switch, 5-14, 5-15
--L--
Late
Chip Select
Logic Example, 10-9
Timing, 10-9
Latency, Interrupt, 8-5
Linpack Benchmark, 5-10, 5-11
Loops, MC68882 Instruction, 5-9
M
Mantissa Sizes, 1-11
Maximum Ratings, 12-1
MC68881
Arithmetic Operation Timing, 8-14
Block Diagram, 1-7
Busy State Frame Format, 6-30
Detail Timing Tabtes, 8-19
FMUL and FMOVE Instruction Concurrency, 5-7
FMUL Instruction Concurrency, 5-2
Idle State Frame Format, 6-30
Instruction Overlap
Example, 8-22, 8-23
Times, 8-40
Take Mid-Instruction Exception Dialog, 7-34
MC68882
Arithmetic Operation Timing, 8-15
Block Diagram, 1-8
Busy State Frame Format, 6-31
Code Optimization, 5-9
Concurrent Operations, 8-13
Exception Handlers, 6-28
External-to-Register Instruction Dialog, 7-24
FMOVE Instruction
Arranging, 5-9
Execution Times, 5-10
FMUL and FMOVE Instruction Concurrency, 5-8
Idle State Frame Format, 6-31
Instruction Loops, 5-9
OPCLASS 010 Instruction Dialog, 7-22
OPCLASS 011 Instruction Dialog, 7.-24
Performance Improvement Example, 5-10
Programming Considerations, 1-16
Register Conflicts, 5-9
Register-to-External Instruction Diatog, 7-26
Take Mid-Instruction Exception Dialog, 7-36,
7-37
Take Pre-lnstruction Exception Dialog, 7-33,
7-34
Mid-Instruction
Exception
Dialog, MC68881, 7-34
Dialog, MC68882, 7-36, 7-37
Primitive, 7-18
Primitive Format, 7-18
Stack Frame, 7-19
Interrupt Dialog, 7-35, 7-38
Middle Phase, 6-38
Minimum
Concurrency Instructions, 5-5
Exception Handler Example, 5-12
FREESCALE
INDEX-6
MC68881/MC68882 USER'S MANUAL
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