FADD FADD
Instruction Format:
15 14 t3
I 1 1
0 R/M 0
12 11 10 9 8 7 6 5 4 3 2 1 0
COPROCESSOR EFFECTIVE
ADORESS
1 ID 0 0 0 MODE REGISTER
SOURCE
DESTINATION
SPECIFIER
REGISTER 0 1 0 0 0 1 0
Instruction Fields:
Coprocessor ID Field -- Specifies which coprocessor in the system is to execute this
instruction. Freescale assemblers default to ID = 1 for the FPCP.
Effective Address Field -- Determines the addressing mode for external operands.
If R/M =0, this field is unused, and should be all zeros.
If R/M = 1, this field is encoded with an M68000 addressing mode as shown:
Addressing Mode Mode Register
Dn* 000 reg. number;Dn
An -- --
(An) 010
reg. number:An
(An)+ 011
reg. number:An
-(An) 100
reg. number:An
(d16,An) 101 I
reg. number:An
(d8,An,Xn) 110
reg. number:An
(bd,An,Xn) 110
reg. number:An
([bd,An,XnJ,od) 110
reg. number:An
([bd,An],Xn,od) 110 reg.
number:An
*Only if <fret> is Byte,
Word, Long, or Single.
Addressing Mode Mode Register
(xxx).W 111 000
(x×x).L 111 001
#<data>
111 100
(d 16,PC) 111 010
(ds,PC,Xn) 111 011
(bd,PC,Xn) 111 011
([bd,PC,Xnl,od) 111 011
([bd,PC],Xn,od) 111 011
R/M Field -- Specifies the source operand address mode.
0 -- The operation is register to register.
1 -- The operation is <ea> to register.
Source Specifier Field -- Specifies the source register or data focmat.
If R/M = 0, specifies the source floating-point data register, FPm.
If R/M = 1, specifies the source data format:
000 L Long Word Integer
001 S Single Precision Real
010 X Extended Precision Real
011 P Packed Decimal Real
100 W Word Integer
101 D Double Precision Real
110 B Byte Integer
Destination Register Field --Specifies the destination floating-point data register, FPn.
MC68881/MC68882 USER'S MANUAL FREESCALE
4-23
To Next Page
Loading...