4
FCMP
Compare
FCMP
Operation:
FPn -- Source
Assembler
FCMP.<fmt> <ea>,FPn
Syntax:
FCMP.X FPm,FPn
Attributes:
Format= (Byte, Word, Long, Single, Double, Extended, Packed)
Description:
Converts the source operand to extended precision {if necessary) and sub-
tracts the operand from the destination floating-point data register. The result of the
subtraction is not retained, but it is used to set the floating-point condition codes as
described in 4.5.5.1 SETTING FLOATING-POINT CONDITION CODES.
Operation
TableThe entries in this operation table differ from those of the tables describing
most of the FPCP instructions. For each combination of input operand types, the
condition code bits that may be set are indicated. If the name of a condition code bit
is given and is not
enclosed
in brackets, then it is always set. If the
name
of a condition
code bit is enclosed in brackets, then that bit is either set or cleared, as appropriate.
If the name of a condition code bit is not given, then that bit is always cleared by the
operation. The infinity bit is always cleared by the FCMP instruction, since it is not
used by any of the conditional predicate equations. Note that the NAN bit is not shown,
since NANs are always handled in the same manner (as described in 4.5.4 NANs).
Source
Destination
In Range +
Zero +
Infinity
In
Range
+
{NZ} none
N {NZ}
N
N
Zero
Infinity
none none non8
N N none
N none Z Z N none
N none NZ NZ N none
Z none
N NZ
none none
N N
none none
N N
NOTE:
Status Register:
Condition Codes:
Quotient Byte:
Exception Byte:
Accrued Exception Byte:
If either operand is a NAN, refer to 4.5.4 NANs for more information.
Affected as described in the operation table above
Not affected
BSUN Cleared
SNAN Refer to 4.5.4
NANs.
OPERR Cleared
OVFL Cleared
UNFL Cleared
DZ Cleared
INEX2 Cleared
INEXl If <fmt> is Packed, refer to 6.1.8 Inexact Result
on Decimal Input; cleared otherwise
Affected as described in 6.1.10 IEEE Exception and Trap Com-
patibility
FREESCALE
4-32
MC68881/MC68882 USER'S MANUAL
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