Intel S7000FC4UR Technical Product Specification

BIOS Initialization Intel® Server System S7000FC4UR
Revision 1.0
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14. BIOS Initialization
14.1 Processors
14.1.1 Multiple Processor Initialization
IA-32 processors have a microcode-based Boot Strap Processor (BSP) arbitration protocol. The
system BSP starts executing from the reset vector (F000:FFF0h). Any processor not performing
the role of system BSP is called an application processor (AP).
The Memory Controller Hub (MCH) supports four processor front side bus (FSB) units, each
accommodating one Quad-Core Intel
®
Xeon
®
processor. At reset, hardware arbitration chooses
one system BSP from the available processor cores on each FSB. The BIOS Power-on Self
Test (POST) code requires only one processor for execution. This requires the BIOS to elect a
system BSP using registers in the MCH. The BIOS cannot guarantee which processor will be
the system BSP, only that a system BSP will be selected.
In the remainder of this document, the system BSP is referred to as the BSP.
The BSP executes the BIOS POST and prepares the server to boot the operating system. At
boot time, the server is in virtual wire mode and the BSP alone is programmed to accept local
interrupts via the INTR signal driven by the 8259 Programmable Interrupt Controller (PIC) and
non-maskable interrupt (NMI) logic.
As a part of the boot process, the BSP wakes each AP. All AP Memory Type Range Register
(MTRR) sets are then programmed identically to the BSP. All APs then execute a halt
instruction with their local interrupts disabled.
The BSP executes CPUID instructions to determine the supported BSP feature set. If the BSP
determines that an AP exists that is a lower-featured processor or that has a lower value
returned by the CPUID function, then the BSP switches to the lowest-featured processor in the
server.
The System Management Mode (SMM) handler expects all processors to respond to a System
Management Interrupt (SMI).
14.1.2 Processor Built-In Self Test (BIST)
The BIOS does not support processor BIST. The BIOS leaves all processor BIST settings in the
processor and chipset set to power on default values.
14.1.3 Processor Cache
The BIOS enables all levels of processor cache. There are no user options to modify the cache
configuration, size, or policies. All detected cache sizes are reported in the SMBIOS Type 7
structures. The largest and highest-level cache detected is reported in the BIOS Setup utility.

Intel S7000FC4UR Specifications

General

Brand	Intel
Model	S7000FC4UR
Category	Server
Language	English