Intel® Server System S7000FC4UR TPS BIOS Initialization
Revision 1.0
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then performance can be slowed due to more cache misses and more time spent filling the
cache lines.
14.1.12 Intel
®
Core Multi-Processing (CMP)
Intel
®
CMP architecture divides the processor core into multiple parts, allowing separate control
of each execution unit and the package with regard to power management. A CMP processor
core consists of independent execution cores and shared logic block.
14.1.12.1 Execution Core Contents
The execution cores consists of:
Instruction fetch/dispatch units
Level 1 cache controllers
Integer/floating point execution units
The shared logic block contains L2 cache controller, bus interface logic and power management
logic.
14.1.12.2 CMP Support
The BIOS takes these steps to support CMP:
Initializes all processor cores
Installs NMI handlers for all multi-core processors
Leaves each AP in CLI/HLT loop after completing processor initialization
Initializes stack for all APs
The BIOS performs these actions when CMP is enabled:
The BIOS POST diagnostic screen displays the total number of logical processors.
Creates a separate ACPI MADT table entry for each logical processor. This causes
Windows Device Manager to display a separate processor icon for all logical processors.
Creates a separate Multiprocessor Specification, Revision 1.4, May 1997, Intel
Corporation table entry for each logical processor
SMBIOS Type 4 structure shows only the physical processors installed. It does not
describe the virtual processors.
14.1.13 Intel
®
Virtualization Technology
Intel
®
Virtualization Technology supports multiple software environments sharing the same
hardware resources. Each software environment may consist of an operating system and
applications. Intel
®
Virtualization Technology can be enabled or disabled in the BIOS Setup
utility. The default behavior is disabled.
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