Intel® Server System S7000FC4UR TPS BMC Functional Specifications
Revision 1.0
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The digital thermal sensors are located on the processor platform environment control interface
(PECI) bus. The BMC does not access this bus directly, but communicates over a SMBus with a
PECI-poller device that polls the digital thermal sensors over the PECI bus.
The IPMI sensor names associated with these devices are P1 Therm Margin, P2 Therm Margin,
P3 Therm Margin and P4 Therm Margin. The default SDR configuration is to have no thresholds
programmed or event generation enabled because the sensor is expected to reach its maximum
value of zero during normal operation.
22.15.3.1 PECI Interface
The platform environment control interface (PECI) is a one-wire, self-clocked bus interface that
provides a communication channel between Intel processors and chipset components to an
external monitoring device. The PECI bus communicates environment information, such as the
temperature data, between the managed components, referred to as the PECI client devices,
and the management controller, referred to as the PECI system host. The PECI standard
supersedes older methods, such as the thermal diode, for gathering thermal data.
The PECI interface consists of a microcontroller with PECI drive circuitry. The BMC monitors the
processor temperature by reading the PECI controller over one of the ESB2’s private I
2
C /
SMBus.
22.15.4 Processor Thermal Control Monitoring (Prochot)
The BMC monitors processor thermal control monitoring for each processor. The LM94*
provides this functionality by reading the percentage of time that the processor ProcHot signal is
asserted over a given measurement window (set to 5.8 seconds).
The BMC implements this as a threshold sensor (IPMI sensor type = processor, sensor name =
Therm Margin) on a per-processor basis. This sensor supports one threshold, the upper-critical,
and it is set for 50% by default in the SDRs. The IPMI sensor names associated with these
devices are P1-P4 Thermal ctrl %.
When the processors are throttled by the Power Safe feature (see section 22.19.5), the Prochot
sensors will show reading/state unavailable status to prevent spurious Prochot-related SEL
events.
22.15.5 CPU Missing Sensor
The BMC verifies at least one processor is installed at start-up. The hardware does not allow
the server to power up if no processor is installed.
At BMC initialization, the CPU missing sensor is first set to a de-asserted state. The BMC then
checks for a missing processor and sets the new value accordingly. If an error is detected and
the SDR is so configured, a SEL event is logged. The BMC checks for this fault condition and
updates the sensor state at each attempt to DC power-on the system. At each DC power-on
attempt, a beep code is generated if this fault is detected. Beep codes are listed in Table 101.
The CPU missing sensor is an auto-re-arm sensor, but it is not re-armed at system DC power-
on or for system resets. To clear the sensor:
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