Intel® Server System S7000FC4UR TPS Baseboard Management Controller (BMC)
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21.1.1 ESB2 Baseboard Management Controller Functionality
The BMC is provided by an embedded ARC* controller and associated peripheral functionality
that is required for IPMI-based server management.
The following is a summary of the ESB2 management hardware features utilized by the BMC:
ARC4 processor with 16 Kbytes instruction cache (I-cache) and data cache (D-cache).
256 kbyte of internal SRAM with dual ports: one for code accesses and one for all other
accesses.
Expansion bus, allowing connection to asynchronous or synchronous external flash
programmable read-only memory (PROM), external SRAM, or external SDRAM. Wait
states are programmable.
Serial flash interface.
Five SMB ports, two that support fast management links (FML), either master or slave
RS-232 serial port (UART).
Cryptographic module, supporting
- Advanced Encryption Standard (AES) algorithm
- Rivest
Cipher 4 (RC4) encryption algorithms
- Secure Hash Algorithm 1 (SHA1) authentication algorithm with internal direct
memory access (DMA) and raw checksum support.
- Message Digest Algorithm 5 (MD5) authentication algorithm with internal direct
memory access (DMA) and raw checksum support.
Keyboard text (KT) interface.
Universal host controller interface (UHCI): USB.
KCS interface mapped to a PCI Express* function.
Two additional KCS interfaces, controlled by the BIOS, and residing on the LPC bus.
General-purpose input/output (GPIO) interface.
Media Access Controller (MAC) control and status register (CSR) interface.
Timer interface.
Host DMA interface.
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