Intel S7000FC4UR Technical Product Specification

Intel® Server System S7000FC4UR TPS BIOS Initialization
Revision 1.0
107
Error BIOS Response
Processor microcode
missing
 Logs the error into the SEL
 Alerts the BMC of the configuration error with the IPMI Set Processor State
command indicating a configuration error for all mismatched processors.
 Does not disable processor
 Displays “816x: Processor 0x unable to apply microcode update” message in
the POST Error Manager.
 Pauses the system for user intervention
Processor FSB speeds not
identical
 Logs the error into the SEL
 Alerts the BMC of the configuration error with the IPMI Set Processor State
command indicating a configuration error for all mismatched processors.
 Does not disable processor
 Displays “0195: Processor Front Side Bus speed mismatch detected”
message in the POST Error Manager.
 Halts the system
14.2 Memory
The chipset Memory Controller Hub (MCH) supports fully-buffered DIMM (FBDIMM) technology.
The integrated MCH on the chipset divides the FBDIMMs on the board into two autonomous
sets called branches.
Each branch has two channels. In dual-channel mode, FBDIMMs on adjacent channels work in
lockstep to provide the same cache line data and a combined ECC. In the single-channel mode
only Channel 0 is active.
The BIOS dynamically configures the memory controller in accordance with the available
FBDIMM population and the selected Reliability, Availability, and Serviceability (RAS) mode of
operation.
14.2.1 Memory Sub-System Nomenclature
The server system complies with the memory subsystem nomenclature guidelines. The
guidelines are in the sections below.
14.2.1.1 Memory Riser Boards
The server system supports four removable memory riser boards. The memory riser board
connectors are silk screened on the main board as follows:
 MEM A
 MEM B
 MEM C
 MEM D

Intel S7000FC4UR Specifications

General

Brand	Intel
Model	S7000FC4UR
Category	Server
Language	English