BIOS Role in Server Management ESB2 BMC Core TPS
Revision 1.0
Intel order number E18291-001
214
Offset Name Length Value Description
22h Part Number Byte String String number for the part number of this
processor. This value is set by the
manufacturer and normally not changeable.
23h Core Count Byte Varies Number of cores per processor socket. If
the value is unknown, the field is set to 0.
See the System Management BIOS
Reference Specification, Version 2.5,
Section 3.3.5.6 for more information.
24h Core Enabled Byte Varies Number of enabled cores per processor
socket. If the value is unknown, the field is
set 0. See the System Management BIOS
Reference Specification, Version 2.5,
Section 3.3.5.7 for more information.
25h Thread Count Byte Varies Number of threads per processor socket. If
the value is unknown, the field is set to 0.
See the System Management BIOS
Reference Specification, Version 2.5,
Section 3.3.5.8 for more information.
26h Processor
Characteristics
Word Bit Field Defines which functions the processor
supports.
18.5.3.6 Type 7 Structure — Cache Information
The SMBIOS Type 7 structure describes the attributes of the processor cache device(s) in the
server. The BIOS dynamically creates one structure per cache device present in the server. For
example, the BIOS creates six Type 7 structures if two processors are installed each supporting
three levels of cache.
Table 76. SMBIOS Type 7 Structure — Cache Information
Offset Name Length Value Description
00h Type Byte 7 Cache information indicator.
01h Length Byte 13h
02h Handle Word Varies
04h Socket
Designation
Byte String String number for Reference Designation
Same as associated processor
05h Cache
Configuration
Word Varies Bits 15:10
0 = Reserved
Bits 9:8
00b = Write through
01b = Write back
10b = Varies with memory address
11b = Unknown
Bit 7
0b = Disabled at boot time
1b = Enabled at boot time
Bits 6:5
00b = Internal
Bit 4
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