Intel S7000FC4UR - Figure 35. Memory Population for Single-Channel with Multiple Fbdimms

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BIOS Initialization Intel® Server System S7000FC4UR

Revision 1.0

114

Figure 35. Memory Population for Single-Channel with Multiple FBDIMMs

This configuration:

 Low-performance mode, and is a fail-safe mode when the DIMMs cannot be lock-

stepped and the system has multiple DIMMs on Memory Riser Boards A and B.

 Default mode if only Memory Riser Board A DIMM slots are populated. See Table 29.

Main Page

Default Chapter2
- Revision History2
- Table of Contents3
1 Introduction23
2 Main Board24
- Introduction24
  - Main Board Block Diagram24
  - Figure 1. Main Board Block Diagram25
- Functional Architecture26
3 Main Board Server Management53
- IPMI 2.0 Features53
- Non IPMI Features54
- Functional Architecture55
- Supported Features61
4 Memory Riser70
- Functional Architecture70
5 I/O Riser76
- I/O Riser Features76
- Functional Architecture77
- Figure 14. I/O Riser Block Diagram77
6 SAS Riser78
- SAS Riser Features78
- Functional Architecture78
7 SAS Backplane81
- System Block Diagram82
- Figure 15. SAS Backplane System Block Diagram82
- Architectural Overview83
  - 3Gbit SAS Port Expanders83
- Functional Architecture84
8 System Overview90
- Figure 18. Intel ® Server System S7000FC4UR (Front View)90
9 System Chassis and Sub-Assemblies99
- Base Chassis and Top Covers99
- Power and Fan Subsystems100
- Main Board Subsystem103
- Peripheral Bay Subsystem103
- Front Bezel105
10 1570W Power Supply106
- 10.1 AC Input Requirement106
- 10.2 DC Output Requirements107
- 10.3 Regulatory Agency Requirements111
11 Power Distribution Board112
- Remote On/Off (-PS_ON)112
- POWER GOOD SIGNAL (POK, or P_GOOD)112
- Figure 30. Power Distribution Board Layout112
- Vin_Good113
12 Front Panel I/O and Control Boards114
- 12.1 Architectural Overview114
- 12.2 Functional Architecture115
- 12.3 Front Panel Control Module116
13 Basic Input/Output System (BIOS)118
- 13.1 BIOS Architecture118
  - Data Structure Descriptions118
- 13.2 BIOS Identification String118
14 BIOS Initialization120
- 14.1 Processors120
- 14.2 Memory129
- 14.3 I/O Subsystem163
- 14.4 Fan Speed Control and Thermal Management170
15 BIOS User Interface173
- Splash Logo Diagnostic Screen173
  - Splash Logo Screen173
  - Diagnostic Screen173
- 15.2 BIOS Setup Utility174
- 15.3 Loading BIOS Defaults215
16 BIOS Update Support216
- 16.1 Rolling BIOS216
- 16.2 OEM Binary217
  - OEM Splash Logo217
  - OEM Strings218
17 Operating System Boot, Sleep, and Wake219
- 17.1 Boot Device Selection219
- 17.2 Operating System Support220
- 17.3 Front Control Panel Support222
- 17.4 Sleep and Wake Support223
  - System Sleep States223
- Non-Maskable Interrupt (NMI) Handling224
- Table 70. NMI Error Messages225
- Ipmi226
- Wired for Management (WFM)230
- Security242
  - Password Clear Jumper243
  - Table 82. Timestamp Clock Sync Format243
19 BIOS Error Handling245
- Fault Resilient Booting245
- POST Progress Codes and Errors257
  - POST Error Manager Messages and Handling260
  - Table 94. POST Error Manager Messages and Handling261
20 New Technologies269
- Physical Presence270
- Internet SCSI (Iscsi)271
21 Baseboard Management Controller (BMC)272
- ESB2 Baseboard Management Controller Functionality273
22 BMC Functional Specifications274
- Power-Up Sequence275
- Power State Retention276
- Table 95. ACPI Power States277
- Advanced Configuration and Power Interface (ACPI)277
- Table 96. System Reset Sources and Actions278
- ACPI Power State Notify278
- Soft Reset and Hard Reset279
- Fault Resilient Booting (FRB)280
- Table 97. Power LED Indicator States281
- Table 98. System Status LED Indicator States281
- Table 99. Chassis ID LED Indicator States283
- Secure Mode and Front Panel Lock-Out Operation284
- Table 100. Secure Mode Vs. ACPI State285
- Set Fault Indication Command285
- System Event Log (SEL)286
- Table 101. BMC Beep Codes287
- SDR Repository Erasure287
- Table 102. NMI Signal Generation and Event Logging288
- Table 103. Processor Sensors289
- General Sensor Behavior289
  - Processor VRD Over-Temperature Sensor290
  - Processor Thermal Control Monitoring (Prochot)291
- Standard Fan Management292
  - Sleep State Fan Control293
  - Interactions with DIMM Thermal Management294
- Power Supply Management Interface (PSMI)295
  - Power Supply Status Sensors296
  - Power Safe297
- System Memory RAS and Bus Error Monitoring298
- Hot-Swap Controller299
- Memory Region Temperature Monitoring300
- LAN Leash Event Monitoring301
23 BMC Messaging Interfaces302
- IPMB Communication Interface303
24 Event Filtering and Alerting307
25 BMC Flash Update308
- On-Line Firmware Update309
26 BIOS-BMC Interactions310
- Sensors312
  - Sensors314
  - Table 104. Sensors315
27 Sensors323
- Figure 71. HSC Interface Routing323
- Table 105. I 2 C Bus Assignements323
28 Hot-Swap Controller (HSC) Architecture323
- GPIO Pins324
- Table 106. Platform Identification325
- Table 107. Bus Adapter Identification325
29 HSC Functional Specifications325
- Table 108. Cable Detect Configuration326
  - Sensor Initialization326
  - HSC FRU Format327
30 HSC IPMB Application and Sensors329
- 30.2.1 Digital and Discrete Sensor Formats331
- 30.3 Event Message Generation331
31 HSC Firmware Update332
- 31.1 HSC Update over IPMB332
Glossary334
Reference Documents342

Intel S7000FC4UR - Figure 35. Memory Population for Single-Channel with Multiple Fbdimms

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