Main Board Intel® Server System S7000FC4UR TPS
Revision 1.0
Intel order number E18291-001
12
Memory riser installed in slot A, with upto 8 DIMMs slot populated (uses the MCH’s
single DIMM/single channel mode).
Memory risers installed in both slot A and B together.
Memory risers installed in all four-riser slots.
Other riser configurations are not supported because they will cause DIMM population violations
and malfunctions in memory riser DIMM fault LED operation.
2.2.7 Main Board I/O Riser Interface
The main board includes a 280 pin PCI-Express* super-slot custom connector to interface with
the I/O riser card. To communicate with the advanced firmware control (Intel
®
Remote
Management Module 2) the I/O riser connector will have the following:
Two FML buses
One USB port
A video DVO interface
A LPC Bus
A RS232 BMC Serial Bus
It also has the PCI-Express x4 Link and Gigabit Lan Link for the Intel
®
82575EB Gigabit
Ethernet Controller.
2.2.8 Main Board SAS Riser Interface
The main board includes a 98 pin x8 pin PCI-Express* connector to interface with the x4 PCI-
Express* SAS Riser card. This PCI-Express* slot is meant for the SAS Riser and is not to be
used with any other type of PCI-Express* Standard Adapter Card
2.2.9 Clock Subsystem
This section describes the Clock Architecture/Sub-system for the main board.
2.2.9.1 Clock Overview
The main board clock tree is generated from a single CK410B with spread spectrum capability.
The CK410B generates multiple copies of differential pair high-speed clocks (266MHz BCLK).
DB1200G* (High BW / PLL mode) buffer generates additional BCLK copies for the CPUs,
XDP1, and MCH core.
The CK410B drives BCLKs to the two DB1900Bs (High BW / PLL mode) for FBD clocking. Each
FBD branch clock input is fed by a DB1900G* buffer. 16 DIMMs are driven by each buffer (8 on
each of two risers). The CK410B also generates 100MHz SRC clocks including an input to a
DB1900G* buffer to I/O subsystems.
The figure below is the main board Clock Block Diagram.
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