BIOS Initialization Intel® Server System S7000FC4UR
Revision 1.0
100
Detects the appropriate SMRAM State Save Map used by the processor
Enables Intel
®
EM64T during memory initialization if necessary
The BIOS does not activate Intel
®
EM64T mode. The system is in IA-32 compatibility mode
when booting to an operating system.
See the Intel
®
Extended Memory 64 Technology BIOS Writer's Guide for more information
about activating and deactivating Intel
®
EM64T mode.
14.1.8 Execute Disable Bit Feature
The Execute Disable Bit feature (XD bit) is an enhancement to the Intel
®
IA-32 architecture. An
IA-32 processor supporting the Execute Disable Bit feature can prevent data pages from being
used by malicious software to execute code. An IA-32 processor with the XD bit feature can
provide memory protection in either of the following modes:
Legacy protected mode if Physical Address Extension (PAE) enabled.
IA-32e mode when 64-bit extension technology is enabled. (Entering IA-32e mode
requires enabling PAE.)
The XD bit does not introduce any new instructions. It requires operating systems to operate in
a PAE-enabled environment and establish a page-granular protection policy for memory. The
XD bit can be enabled and disabled in BIOS Setup. The default behavior is enabled.
14.1.9 Enhanced Halt State (C1E)
All processors support the Halt State (C1) through the native processor instructions HLT and
MWAIT. Some processors implement an optimization of the C1 state called the Enhanced Halt
State (C1E) to further reduce the total power consumption while in C1.
When C1E is enabled, and all logical processors in the physical processors have entered the
C1 state, the processor reduces the core clock frequency to system bus ratio and VID. The
transition of the physical processor from C1 to C1E is accomplished similar to an Enhanced
Intel SpeedStep
®
Technology transition. If the BIOS determines all the system processors
support C1E, then it is enabled.
14.1.10 Hardware Prefetch
The automatic hardware prefetch unit operates transparently without requiring programmer’s
intervention. It is triggered by regular access patterns and helps predict future access thereby
overlapping memory latency with computation. By enabling concurrency between memory
accesses and computation, the computational benefit of higher processor frequencies is
maximized.
14.1.11 Adjacent Cache Line Prefetch
Cache lines can be fetched one at a time, or by enabling Adjacent Cache Line Prefetch the
cache lines are fetched in pairs. This can be helpful if the data would continue to the next cache
line, causing less cache misses to maximize throughput. When the data is not in adjacent lines,
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