BIOS Error Handling ESB2 BMC Core TPS
Revision 1.0
Intel order number E18291-001
226
19.2.2.1.2 Machine Check Errors
The BIOS clears all machine check error status banks on a power good reset and enables all
machine check errors during POST.
The BIOS installs a default machine check handler during POST for legacy operating systems.
This default handler resets the system in response to machine check events during runtime. It is
assumed most operating systems install their own machine check handler.
The BIOS does not report machine check errors.
19.2.2.2 Memory Errors
The hardware generates an SMI on both uncorrectable and correctable data errors in the
memory array. Uncorrectable errors may corrupt the contents of SMRAM. The BIOS SMI
handler logs the error and the failing FBDIMM number to the BMC if the SMRAM contents are
still valid. The ability to isolate the failure down to a single FBDIMM may not be available on
certain errors and/or during early POST.
19.2.2.3 Legacy PCI and PCI-X* Errors
The traditional PCI bus is a parallel bus mechanism that provides two sideband signals for error
reporting. The PERR# signal reports parity errors and the SERR# signal reports all other system
errors.
PCI data parity errors are not considered intrinsically fatal because the PCI bus master has the
option to retry the offending transaction. The BIOS correspondingly logs a PERR SEL entry but
does not halt the system. If the bus master cannot retry or if the retry fails, then the hardware
escalates the error to a fatal SERR# event. All other PCI-related errors are considered fatal and
reported by SERR#. The BIOS handles SERR events by generating a SERR SEL entry and
then triggers either a Non-Maskable Interrupt or system reset based on the BIOS Setup utility
option ‘Reset on Fatal Error’.
The BIOS configures all PCI-to-PCI bridges so they generate SERR# on the primary interface
whenever an SERR# assertion is detected on the secondary/downstream side.
The server system does not support 32-bit PCI slots. The only traditional, 32-bit PCI device is
the ATI embedded video* on a dedicated 32-bit legacy PCI bus controlled that the Intel
®
ESB2
controls. Video parity errors are not generally considered critical so the server system wires the
PERR# signal on this bus to a pull-up connector providing a no connect functionality. PERR is
not reported on the legacy PCI bus.
The server system does not have PCI-X* slots or embedded devices. However, it is expected
that the system may be used with first generation PCI Express* adapters that are commonly
organized as a PCI-X device behind a PCI Express to PCI-X bridge.
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