Main Board Intel® Server System S7000FC4UR TPS
Revision 1.0
Intel order number E18291-001
14
The CK410B supports SSC (Spread Spectrum Clocking), but only for FSB host clocks and
SRCs (Serial Reference Clocks). The CK410B supplies the following:
Four host clocks
Five 100 MHz differential SRCs (Serial Reference Clocks)
One 48 MHz USB clock
Seven 33 MHz clocks
Two 14 MHz clocks
On the main board, the CK410B is configured as follows:
(1) BCLK differential pair to DB1200G* differential clock buffer driving Chipset
components at 1:1 ratio. BCLK output frequencies can be set with stuffing options.
(Default = 266MHz)
(2) BCLK differential pairs to two DB1900G* differential clock buffer parts (FBD memory
risers Branch 1 and 2, and Chipset XDP).
(5) SRC PCI-Express* clocks (100MHz) to MCH, DB1900G* differential clock buffer
(PCI-Express*), and Enterprise Southbridge 2 (2 PCI-Express* and 1 SATA)
(1) 48MHz clock for Enterprise Southbridge 2 USB controller
(7 w/1 shared) 33MHz clocks to Enterprise Southbridge 2, TPM, SIO, Video, PLD, FWH
(OEM), and I/O Riser. In order to support eight devices with seven clocks, one of the
clocks is double loaded.
(2) 14MHz clock to Enterprise Southbridge 2, and SIO (OEM).
2.2.9.3 DB1200G* (CPU Clock Buffer)
The DB1200G* is a differential clock buffer supporting the CPU, chipset, and CPU XDP clocks
for the main board. It receives its input source from one of the CK410B processor host clocks.
The DB1200G* provides 12 differential outputs with gear ratio capability.
The main board only uses six outputs at a gear ratio of 1:1. DB1200G* part was selected for its
ability to take clock input w/ freq >200MHz. On the main board, the DB1200G* is configured as
follows:
PLL Mode / High BW
Four host clock differential pairs to four CPUs
One host clock differential pair to XDP1 (CPUs)
One host clock differential pair to MCH (MCH)
Differential routing for the outputs for the CPUs are matched to within 5 mils from clock to clock.
Routing for MCH clock is matched to the other CPUs lengths plus +0.7 inch. XDP clock routing
has no clock-to-clock length matching requirements.
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