Intel® Server System S7000FC4UR TPS Main Board
Revision 1.0
29
2.2.23.3 Reset and Clock Enabling Sequence
1. Chipset (Intel
®
7300 Chipset MCH and Enterprise Southbridge 2) and processors are
powered as indicated by corresponding VR Power Goods.
2. On-die power-detect circuitry initiates PLL locking. However, the absence of a reference
clock at PLL input triggers the low frequency detect circuit, which shuts the PLL off.
3. Once all VRs have achieved powergood, the PLD asserts CK410B_PWRGD_N low.
This brings all of the clock chips out of their power down states.
4. After its PLL has locked (approximately 1.8ms maximum), the CK410 drives reference
clocks to all of the downstream differential buffers.
5. Upon receiving a PCI-Express* reference clock, the DB1900G* PCI-Express* (in PLL
Bypass Mode) immediately passes this to its outputs (approximately 2.5ns – 4.5ns).
6. Upon receiving a host reference clock, the DB1200G*-Host (in PLL Mode) takes
approximately 1.8ms (maximum) before its PLL locks. Any clock chips in PLL Mode will
drive output clocks only after their PLLs have locked. This is to ensure that unstable
clocks are not driven to downstream devices.
7. Although receiving an FBD reference clock, the FBD branch clock chips (DB1900G*
FBD BR0 and DB1900G* FBD BR1) are held off by an Enterprise Southbridge 2(ICH6)
GPO (GPIO[34], FBD_CLKEN_N) until the appropriate gear ratios can be set.
8. Presence of reference clocks at the chipset and processors (except for FBD devices) are
detected by the low frequency detect circuits. PLL locking is then re-initiated.
9. Chipset and processor PLLs lock and some time later they receive an external
SYS_PWRGD, allowing I/O transactions to commence.
10. FBDIMMs are still in reset and FBD clocks are still disabled. FBDIMMs are kept in reset
by BIOS driving high (“1”) on Enterprise Southbridge 2 (ICH6) GPO (GPIO[33],
FBD_RESET). FBD clocks are kept disabled by BIOS driving high (“1”) on Enterprise
Southbridge 2(ICH6) GPO (GPIO[34], FBD_CLKEN_N).
11. Once BIOS is ready (undefined amount of time), it will detect the FSB host clock speed,
and then detect the FBD clock speed from the FBDIMM SPDs.
12. Based on these speeds, BIOS will select the appropriate gear ratios in the DB1900G*
FBD branch clocks. The internal PLLs will lock within 500 us of initial gear setting
(regardless of OE# assertion). BIOS will provide a minimum 1ms delay before asserting
the Clock Enable GPO low (“0”), thereby releasing the FBD memory clocks.
13. BIOS will then provide a minimum 2.25ms delay between the assertion of clock enable
GPO and the de-assertion of the memory reset GPO to ensure that the memory clocks
will be fully stable.
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