February, 2008
6-40
WorkCentre 5225, 5230
IIT NVM List
Launch Version
General Procedures
715-663 Threshold for 2F AE Control 16 0~255 Value to be compared with the HAE background density when deciding whether to select 2-side AE.
When the background density of HAE is less than the value in this NVM, 2-side AE is not selected.
715-664 Mode Control of 2F AE 0 0~3 0: Conduct 2-side AE control, 1: Selection of 1-side AE is enforced (L0), 2: Output of 2-side AE is
enforced (L1)
715-668 Control of 2C Copy 0 0~1 2-color copy reproduction control. 0: Normal (same as Imari-MF), 1: 1301a series (yellow is not re-
created)
715-669 Control of Tracing Paper Mode 0 0~1 0:,Normal, 1: Tracing Paper mode (*applies to PreIPS C mode as well)
715-680 CL Balance Def Y / Low Density 4 0~8 Default Color Balance Adjustment Level Y Color Low Density
715-681 CL Balance Def Y / Medium Density 4 0~8 Default Color Balance Adjustment Level Y Color Medium Density
715-682 CL Balance Def Y / High Density 4 0~8 Default Color Balance Adjustment Level Y Color High Density
715-683 CL Balance Def M / Low Density 4 0~8 Default Color Balance Adjustment Level M Color Low Density
715-684 CL Balance Def M / Medium Density 4 0~8 Default Color Balance Adjustment Level M Color Medium Density
715-685 CL Balance Def M / High Density 4 0~8 Default Color Balance Adjustment Level M Color High Density
715-686 CL Balance Def C / Low Density 4 0~8 Default Color Balance Adjustment Level C Color Low Density
715-687 CL Balance Def C / Medium Density 4 0~8 Default Color Balance Adjustment Level C Color Medium Density
715-688 CL Balance Def C / High Density 4 0~8 Default Color Balance Adjustment Level C Color High Density
715-689 CL Balance Def K / Low Density 4 0~8 Default Color Balance Adjustment Level K Color Low Density
715-690 CL Balance Def K / Medium Density 4 0~8 Default Color Balance Adjustment Level K Color Medium Density
715-691 CL Balance Def K / High Density 4 0~8 Default Color Balance Adjustment Level K Color High Density
715-692 BW-PH Lighter3 Density 0 0~64 Fine adjustment for density. Coefficient value is calculated by dividing the set value by 64. Values
between 0 and 64 can be set. 0 is handled as 64.
715-693 BW-PH Lighter2 Density 0 0~64 Fine adjustment for density. Coefficient value is calculated by dividing the set value by 64. Values
between 0 and 64 can be set. 0 is handled as 64.
715-694 BW-PH Lighter1 Density 0 0~64 Fine adjustment for density. Coefficient value is calculated by dividing the set value by 64. Values
between 0 and 64 can be set. 0 is handled as 64.
715-702 PLTN/Belt FS Reduce/Enlarge Adjustment 50 0~100 Fine adjustment for Fast Scan Direction Reduce/Enlarge ratios. Specify within the range of 0 and
100 in increments of 1. The value indicates the fine adjustment with 0=-5%, 50=0% and 100=5% at
+/-5% (0.1% increments). (No adjustment in Factory Settings)
715-703 CVT FS Reduce/Enlarge Adjustment 50 0~100 Fine adjustment for Fast Scan Direction Reduce/Enlarge ratios. Specify within the range of 0 and
100 in increments of 1. The value indicates the fine adjustment with 0=-5%, 50=0% and 100=5% at
+/-5% (0.1% increments). (No adjustment in Factory Settings)
715-704 IPS Through Setting1 0 0~65535 IPS Through Setting 1. Force to skip Image Processing functions at memory sample scan. Change
a value at S/W & H/W DEBUG. Always set “0” in normal use. (Handle with care) --The usage is as
follows: Whether to execute/force to skip functions is assigned to each bit. However, you can spec
-
ify multiple bits at a time. [PF1/SHIPS]| [PF2],D'0: AES | BEXG_TH,D'1: DF39 | FSRE_TH,D'2: SSR
| SSR_TH,D'3: FSRE | NSP_TH,D'4: NSP | AER_TH,D'5: 4DLUT | TRC2_TH,D'6: 5AER |
ED_TH,D'7: 5MUL | SEL_TH,D'8: 5MWA | SEL2_TH,D'9: 4AER | (spare),D'10: 4MUL | (spare),D'11:
TRC | (spare),D'12: ED | (spare),D'13: DIRECT | (spare),D'14: AMAOSEL (SHIPS) | (spare),D'15:
(spare) | (spare) The specified bit value is: B'0: Unchanged, B'1: Forced to skip.
715-705 IPS Through Setting2 0 0~65535 IPS Through Setting 2. Sets the bypass mode for 4DLUT. Valid only when 4DLUT is set to be forc-
ibly bypassed at “IPS Bypass Setting 1”. Value is changed at the time of S/W & H/W debug. 0: Data
from Y block bypass L*a*b*, 1: Data from M block bypass L*a*b*, 2: Data from C block bypass
L*a*b*, 3: Data from K block bypass L*a*b*, 4: Data from YMCK blocks bypass L*, 5: Data from
YMCK blocks bypass a*, 6: Data from YMCK blocks bypass b*, 7 to 65535: 0 output
Table 2 IISS
Chain-Link Content Default Range Meaning
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