FMOD Modulo Remainder FMOD
UNFL Refer to 6.1,5 Underflow.
DZ Cleared
INEX2 Refer to 6.1.7
Inexact Result,
INEX1 If <fret> is Packed, refer to 6.1.8 Inexact Result
on
Decimal Input; cleared
otherwise.
Accrued Exception Byte: Affected as described in 6.1.10
IEEE Exception and
Trap Com-
patibility
Instruction Format:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 O
COPROCESSOR EFFECTIVE ADDRESS
1 1 1 1
ID 0 0 0 MODE REGISTER
SOURCE DESTINATION I I
0 RiM 0 SPEC,FIER REGISTER 0 1 O 0 O 0 1
Instruction Fields:
Coprocessor ID Field -- Specifies which coprocessor in the system is to execute this
instruction. Freescale assemblers default to ID = 1 for the FPCP.
Effective Address Field -- Determines the addressing mode for external operands.
If R/M =0, this field is unused, and should be all zeros.
If R/M = 1, this field is encoded with an M68000 addressing mode as shown:
Addressing Mode Mode Register Addressing Mode Mode { Register
Dn* 000 reg. number:Dn (xxx).W 111 O00
An -- -- (xxx).L 111 001 .
iAn) 010 reg. number:An #<data> 111 100
(An)+ 011 reg. number:An
-(An) 100 reg. number:An
(d16,An) 101 reg. number:An (d16,PC) 111 010
(ds,An,Xn) 110 reg. number:An (d8,PC,Xn) 111 011
(bd,An,Xn) l't0 reg.
number:An
(bd,PC,Xn) 111 011
([bd,An,Xn],od) 110 reg. number:An ([bd,PC,Xn],od) 111 011
([bd,AnJ,Xn,od)
110 reg, number:An ([bd,PC),Xn,od) 111 011
*Only if <fmt> is Byte, Word, Long, or Single.
R/M Field -- Specifies the source operand address mode.
0 -- The operation is register to register.
1 -- The operation is <ea> to register.
Source Specifier Field -- Specifies the source register or data format.
• If R/M--0, specifies the source floating-point data register, FPm.
If R/M = 1, specifies the source
data
format:
000 L Long Word Integer
001 S Single Precision Real
010 X Extended Precision Real
011 P Packed Decimal Real
100 W Word Integer
101 D Double Precision Real
110 B Byte Integer
Destination Register Field- Specifies the destination floating-point data register, FPn.
MC68881/MC68882 USER'S MANUAL FREESCALE
4-63
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