4
FMOVEM .ove
Multiple Control Registers
FMOVEM
Operation:
Register List j Destination
Source 0 Register List
Assembler
FMOVEM.L <list>,<ea>
Syntax:
FMOVEM.L <ea>,<list>
<list>
Attributes:
Size = (Long)
A list of any combination of the three floating-
point system control registers (FPCR, FPSR and
FPIAR) with individual register names sepa-
rated by a slash (/).
Description:
Moves one or more 32-bit values into or out of the specified system control
registers. Any combination of the three system control registers may be specified.
The registers are always moved in the same order, regardless of the addressing mode
used; with the FPCR moved first, followed by the FPSR, and the FPIAR moved last (if
a register is not selected for the transfer, the relative order of the transfer of the other
registers is the same). The first register is transferred between the FPCP and the
specified address, with successive registers located up through higher addresses.
When more than one register is moved, the memory or memory-alterable addressing
modes are allowed as shown in the addressing mode tables. If the addressing mode
is predecrement, the address register is first decremented by the total size of the
register images to be moved (i.e., four times the number of registers) and then the
registers are transferred starting at the resultant address. For the postincrement ad-
dressing mode, the selected registers are transferred to or from the specified address,
and then the address register is incremented by the total size of the register images
transferred. If a single system control register is selected, the data register direct
addressing mode may be used; or, if the only register selected is the FPIAR, then the
address register direct addressing mode is allowed. Note that if a single register is
selected, the opcode generated is the same as for the FMOVE single system control
register instruction.
Status Register:
Is changed only if the destination list includes the FPSR; in which case
all bits are modified to reflect the value of the source register image.
Instruction Format:
15 14 13
1 I !
1 0 dr
12 11 10 9
8 7 6 5 4 3 2 1 O
COPROCESSOR I EFFECTIVE ADDRESS
t ID 0 0 J 0 MODE ! F.EGIS'I~,~
REGISTER J 0 f ]
LIST 0 0 0 0 0 l 0 . 0 I C i Q
Instruction Fields:
Coprocessor ID Field -- Specifies which coprocessor in the system is to execute this
instruction. Freescale assemblers default to ID = 1 for the FPCP.
Effective Address Field -- Determines the addressing mode for the operation:
FREESCALE
4-78
MC68881/MC68882 USER'S MANUAL
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