Freescale Semiconductor MC68881 - Page 15

LIST OF ILLUSTRATIONS (Concluded)
Figure Page
Number Title Number
7-35 Take Mid-Instruction Exception Dialog -- MC68882
with No BSET Instruction in the Handler ..................................... 7-37
7-36 Mid-Instruction Interrupt Dialog ................................................... 7-38
7-37 Take BSUN Exception Dialog... .................................................... 7-38
7-38 Take F-Line Emulator Exception Dialog .......................................... 7-39
7-39 FSAVE Format Exception Dialog ................................................... 7-40
7-40 FRESTORE Format Exception Dialog ............................................. 7-41
8-1 Nonconcurrent Instruction Execution, Interrupts Allowed ................... 8-6
8-2 Best-Case Coprocessor Interface Overhead Timing ........................... 8-8
8-3 Worst-Case FPCP Interface Overhead Timing ............ . ..................... 8-9
8-4 Instruction Overlap Examples -- FMOVE.X FPm,FPn ......................... 8-22
8-5 Instruction Overlap Example -- FMOVES.S (An),FPn ......................... 8-23
9-1 MC68881/MC68882 Input/Output Signals
........................................ 9-1
9-2 Sense Device Circuit Example ..................... . ................................ 9-5
10-1 FPCP Data Bus Bit Assignments ................................................... 10-2
10-2 Data Bus Activity vs Port Size and Operand Alignment ..................... 10-2
10-3 FPCP Reset Logic Example .......................................................... 10-6
10-4 Example of Early Chip Select Circuits ......................................... ... 10-8
10-5 Example of Late Chip Select Circuit .............................................. 10-9
10-6 Synchronous Read Cycle Timing Diagram ...................................... 10-10
10-7 Asynchronous Read Cycle Timing Diagram .................................... 10-12
10-8 Asynchronous Write Cycle Timing Diagram .................................... 10-13
11-1 ~ 32-Bit Data Bus Coprocessor Connection
........................................ 11-1
11-2 16-Bit Data Bus Coprocessor Connection ......................................... 11-2
11-3 8-Bit Data Bus Coprocessor Connection ......................................... 11-3
11-4 16-Bit Data Bus Peripheral Processor Connection ............................. 11-4
11-5 8-Bit
Data Bus Peripheral Processor Connection .............................. 11-5
12-1 Clock Input Timing Diagram .............. . ......................................... 12-3
12-2 Asynchronous Read Cycle Timing Diagram .................................... Foldout 1
12-3 Asynchronous Write Cycle Timing Diagram .................................... Foldout 2
12-4 Synchronous Read Cycle Timing Diagram ...................................... Foldout 3
MC68881/MC68882 USER'S MANUAL FREESCALE
XV