Freescale Semiconductor MC68881

Exception Status/Enable Byte24

MC68881/MC68882 Programming Model24

Accrued Exception Byte25

Condition Code Byte25

Mode Control Byte25

Quotient Byte25

Typical Coprocessor Configuration26

MC68881 Simplified Block Diagram27

MC68882 Simplified Block Diagram28

Exponent and Mantissa Sizes31

Condition Code Versus Result Data Type41

Infinities47

Format of Normalized Numbers48

Not-A-Numbers49

Binary Real Data Summary50

Packed Decimal Real Data Format50

Format of Not-A-Numbers50

Internal Data Format51

3,5.1 Conversion to Extended Precision Data Format52

Intermediate Result Format52

Format Conversions52

Conversions to Other Data Formats53

Data Format Details53

Single Precision Binary Real Format54

Double Precision Binary Real Format55

Extended Precision Binary Real Format56

Packed Decimal Real Data Format Detail57

Decimal String Type Definitions57

Instruction Description Conventions59

Instruction Groups59

Data Movement Operations60

Dyadic Operations60

Dyadic Operation Format60

Monadic Operations61

Program Control Operations62

Computational Accuracy63

System Control Operations63

Arithmetic Instructions64

Transcendental Instructions65

Conditional Test Definitions66

Decimal Conversions66

IEEE Nonaware Tests67

IEEE Aware Tests69

Addressing Modes70

Detailed Instruction Descriptions70

Miscellaneous Tests70

Instruction Description Format71

Operation Post Processing73

Individual Instruction Descriptions75

General Type Instruction Command Word Fields184

Register Field Encoding185

Extension Field Encoding for Arithmetic Operations186

Source Format Field Encoding187

Destination Format Field Encoding188

Extension Field Encoding189

Encoding for Move Fpcr Operations190

Encodings for Move Multiple Fpn Operations192

Conditional Predicate Evaluation Responses194

Effective Address Field Encoding Summary197

Conditional Predicate Field Encoding Summary198

MC68881 Concurrency - - FMUL Instruction210

Minimum-Concurrency Instructions213

Monadic Instructions213

Dyadic Operations214

Fully-Concurrent Instructions214

Partial-Concurrency Instructions214

Conditional Instructions215

FMOVE Instruction Execution Times218

Optimized Linpack Loop219

State Frame Sizes219

MC68881/MC68882 Exception Vector Assignments228

EXC and ENABLE Byte Bit Assignments229

Possible Operand Errors232

Possible Divide-By-Zero Exceptions238

BIU Flag Bit Definitions259

MC68881/MC68882 Responses to Save Command260

MC68881/MC68882 Format Word Definitions261

MPU CPU Space Type Field Encoding266

Coprocessor Interface Register Characteristics267

Null Primitive Encodings276

Coprocessor Valid Effective Address Codes278

Evaluate Effective Address and Transfer Data Primitive Encoding278

MC68881/MC68882 Primitive Responses284

Effective Address Calculations319

MC68881 Overall Execution Times320

MC68882 Overall Execution Times321

Timing Calculation Example322

Move Control Register and MOVEM Execution Times323

Instruction Start-Up Times331

Input Operand Conversion334

Arithmetic Calculation Times - - Dyadic Operations336

Rounding and Exception Handling339

Arithmetic Calculation Times - - Monadic Operations340

Output Operand Conversion341

Output Operand Conversion - - Binary Real Formats341

Rounding Operation Time Values341

Exception Processing Time Values345

Data Transfer and Size Acknowledge (DSACK0, DSACK1)349

Signal Summary353

Bus Operation355

Basic Transfer Mechanism Overview355

Bus Cycle Functional Descriptions361

Coprocessor Interface Protocol Restrictions369

16-Bit Data Bus Peripheral Processor Connection373

M a X I M U M Ratings377

DC Electrical Characteristics378

AC Electrical Characteristics - - Clock Input379

AC Electrical Characteristics = - Read and Write Cycles380

Ordering Information and Mechanical Data383

Standard MC68881/MC68882 Order I N F O R M a T I O N383

Pin Assignments384

Package Dimensions385

F P C P Vector Numbers404

Freescale Semiconductor MC68881 - Page 16

Table of Contents

Related product manuals