Freescale Semiconductor MC68881 - Page 152

4
FSCALE Scale Exponent FSCALE
DZ Cleared
INEX2 Cleared
INEX1 If <fret> is Packed, refer to 6.1.8 Inexact Result
on Decimal Input; cleared otherwise.
Accrued Exception Byte: Affected as described in 6.1.10 IEEE Exception and Trap
Compatibility
Instruction Format:
15 14 13 12 11 10 9 8 7 6
. COPROCESSOR
1 1 1 1 ID 0 0 O
SOURCE DESTINATION
0 RIM 0 SPECIFIER REGISTER 0
5 4 3 2 1 0
EFFECTIVF~ ADDRESS
MODE | REGtSFER
o o 1 i 1
Instruction Fields:
Coprocessor ID Field -- Specifies which coprocessor in the system is to execute this
instruction. Freescale assemblers default to ID = 1 for the FPCP.
Effective Address Field -- Determines the addressing mode for external operands.
If R/M =0, this field is unused, and should be all zeros.
If R/M = 1, this field is encoded with an M68000 addressing mode as shown:
Addressing Mode
On*
An
(An)
(An)+
-(An)
(d16,An)
(ds,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,AnJ,Xn,od)
Mode Register
000 reg. number:Dn
010 reg. number:An
011 reg. number:An
100 reg. number:An
101 reg. number:An
110 reg. number:An
110 reg. number:An
110
reg. number:An
110
reg. number:An
*Only if <fmt> is Byte, Word, Long, or Single.
Addressing Mode Mode Register
(xxxI.W 111 033
(xxx}.L 111 031
#<data > 111 !C3
(d16,PC) 111 010
(d8,PC,Xn} 111
011
(bd,PC,Xn} 111 011
(ibd,PC,Xn],od) 111 01t
(lbd,PCJ,Xn,od} 111 01
FREESCALE
4-94
MC68881/MC68882 USER'S MANUAL