Freescale Semiconductor MC68881 - Page 163

FSINCOS Simultaneous Sine and Cosine FSINCOS
INEX1 If <fmt> is Packed, refer to 6.1.8 Inexact Result
on Decimal
Input; cleared otherwise.
Accrued Exception Byte: Affected as described in 6.1.10 IEEE Exception and Trap
Compatibility
Instruction Format:
15 14 13 12 11 10 9 . 8 7 6 5 4 3 2 1 0
COPROCESSOR 1 EFFECTIVE ADDRESS
! 1 1 1 ID 0 I 0 0 MODE REGISTER
SOURCE DESTINATION DESTINATION
0 R/M 0 SPECIFIER REGISTER, FPs 0 1 1 0 REGISTER, FPc
Instruction Fields:
Coprocessor ID Field -- Specifies which coprocessor in the system is to execute this
instruction. Freescale assemblers default to ID = 1 for the FPCP.
Effective Address Field -- Determines the addressing mode for external operands.
If R/M=O, this field is unused, and should be all zeros.
If R/M = 1, this field is encoded with an M68000 addressing mode as shown:
Addressing Mode Mode Register
Dn* 000 reg. number:Dn
An -- --
(An) 010 reg. number:An
(An)+ 011 reg. number:An
-IAn) 100 reg. number:An
(d16,An) 101 reg. number:An
(ds,An,Xn) 110 reg. number:An
(bd,An,Xn) 110 reg. number:An
([bd,An,Xn],od) 110 reg. number:An
([bd,AnJ,Xn,od) 110 reg. number:An
*Only if <fmt> is Byte, Word, Long, or Single.
Addressing Mode Mode Register
(xxx).W 111 O0O
(xxx).L 111 001
#<data> 111 100
(d16,PC) 111 010
(d8,PC,Xn) 111 011
(bd,PC,Xn) 111 011
([bd,PC,Xn},od) 111 011
(Jbd,PCJ,Xn,od) 111 011
R/M Field -- Specifies the source operand address mode.
0 -- The operation is register to register.
1 --The operation is <ea> to register.
Source Specifier Field -- Specifies the source register or data format.
If R/M--O, specifies the source floating-point data register, FPm.
If R/M = 1, specifies the source data format:
000 L Long Word Integer
001 S Single Precision Real
010 X Extended Precision Real
011 P Packed Decimal Real
100 W Word Integer
101 D Double Precision Real
110 B Byte Integer
MC68881/MC68882 USER'S MANUAL FREESCALE
4-105