7.2.3 Save ClR ($04)
This 16-bit read-only register is used by the main processor to issue a context
save
com-
mand to the FPCP, and by the FPCP to return the format word of the FPCP state frame to
the main processor. A read of this register causes any operation that may be executing
(except a state save or restore) to be suspended, and a state save operation is initiated.
Following the read of a not-ready, come-again format word from the save CIR, the next
expected access is a read of the save CIR. After the read of an idle or busy format word,
the next expected access is to the operand CIR (to transfer the state frame). After the read
of a null format word, the FPCP is in the reset state, and the next expected access is to the
command or condition CIR.
The only time tllat a read of this register is illegal is when the FPCP is executing a state
frame transfer for an FSAVE or FRESTORE instruction; a read of the save CIR is legal at
any other time. If the main processor reads the save CIR at an illegal time, the invalid
format word is returned. In response to the invalid format word, the main processor can
write an abort to the FPCP to return it to the idle
state.
7.2.4 Restore ClR ($06)
This 16-bit read/write register is used by the main processor to issue a context restore
command to the FPCP and to validate the format word of a state frame. A write of this
register causes the FPCP to immediately stop any operation that may be executing and
prepare to load a new internal state context from a memory-resident state frame.
After the main processor writes a format word to the restore CIR, it must read the restore
CIR to receive the result of the format word verification. If the written format wora is valid,
that format word is read back from the restore CIR to indicate the successful verification.
If the format word is invalid, the invalid format, take exception value is placed in the restore
CIR to indicate the verification failure. After a successful verification is signaled, the next
expected access is to the operand CIR (to transfer the state frame). After a verification
failure is signaled, the main processor should write an abort to the control CIR in order to
return the FPCP to the idle state. (The MPU does this automatically.)
7.2.5 Operation Word CIR ($08}
This 16-bit write-only register is not used by the FPCP. The only time that this CIR location
is used by the M68000 Family coprocessor interface is when a coprocessor issues the
transfer operation word primitive, in which case the main processor writes the F-line word
of the instruction to the operation word CIR. Since the FPCP never issues the transfer
operation word primitive, the operation word CIR location should never be written by the"
main processor. If a write to this location occurs, it is ignored; it does not cause a protocol
violation.
7.2.6 Command ClR ($0A)
This 16-bit write-only register is used by the main processor to initiate the dialog for a
general type coprocessor instruction. When the FPCP detects a write to this CIR location,
MC68881/MC68882 USER'S MANUAL
FREESCALE
7-5
To Next Page
Loading...