7
the data value is latched from the data bus. If the MC68881 is executing a previous instruc-
tion in the APU or if the CU of the MC68882 is still busy when the command CIR is written,
thelatched command word is saved for later use, and the response CIR is encoded with
the null (CA--- 1, IA= 1) primitive. If the FPCP is in the idle or reset state when a write to
the command CIR occurs, it encodes the first primitive for the selected instruction dialog
in the response CIR in order to begin the execution of the new instruction.
A write to this CIR location is legal at any time except when the FPCP is in the initial phase
of a general instruction or before the read of the conditional evaluation for a previous
conditional instruction. If a write to the command CIR occurs when it is not expected, a
protocol violation occurs, and the command word that is written is not saved by the FPCP.
7.2.7 Condition ClR ($0E)
This 16-bit write-only register is used by the main processor to initiate the dialog for a
conditional type coprocessor instruction. When the FPCP detects a write to this CIR location,
the data value is latched from the data bus. If the FPCP is executing a previous instruction
when the condition CIR is written, the latched conditional predicate is saved for later use,
and the response CIR is encoded with the null (CA=l, IA=I) primitive, if the FPCP is in
the idle or reset state when a write to the condition CIR occurs, it evaluates the selected
condition and returns the null (CA = 0, TF = x) primitive (where the TF bit indicates whether
the conditional evaluation is true (1) or false (0)).
A write to this CIR location is legal at any time except when the FPCP is in the initial phase
of a general instruction, or before the read of the conditional evaluation for a previous
conditional instruction. If a write to the condition CIR occurs when it is not expected, a
protocol violation occurs, and the conditional predicate that is written is not saved by the
FPCP.
7.2.80perand CIR ($10)
This 32-bit read/write register is used by the main processor to transfer data to and from
the FPCP. The FPCP transfers data through this CIR location in the following cases:
1. Following an evaluate effective address and transfer data primitive
2. Following the read of the register select CIR after a transfer multiple coprocessor
registers primitive
3. Following a transfer single main processor register primitive
4. Following a read of an idle or busy format word from the save CIR
5. Following a write of an idle or busy format word to the restore CIR
These five cases are the only times when an access to the operand CIR is legal. At any
other time, an access to this CIR location causes a protocol violation.
The FPCP expects all operands that are to be transferred through this CIR location to be
aligned with the most significant byte of the register. Any operand larger than four bytes
is transferred through this register using a sequence of long-word transfers. If the operand
is not a multiple of four bytes in size, the portion remaining after the initial long-word
FREESCALE
7-6
MC68881/MC68882 USER'S MANUAL
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