an instruction. Also, it is assumed that when the MPU is waiting for the FPCP during a
nonconcurrent instruction, the main processor reads the response register at exactly the
moment when the FPCP is prepared to return a service request primitive to complete or
continue the instruction. If these conditions are not met, the actual instruction execution
time can be shorter or longer than the values shown in the tables, due to synchronization
of the two devices.
First, it must be noted that the FPCP does not begin execution of an instruction until the
start of the read cycle from the response CIR in which the first primitive of the instruction
dialog is returned to the main processor. If the MPU attempts to initiate a floating-point
instruction before the previous one has completed and the coprocessor is ready, the FPCP
queues the command word or conditional predicate and then instructs the MPU to wait
(by encoding the null (CA= 1, IA=I) primitive in the response CIR) until the previous
instruction is completed and the FPCP is ready to begin the next instruction. When the
previous instruction has completed execution, the FPCP does not begin execution of the
queued instruction until the next read of the response CIR. The sequence of events for this
situation is:
1. The FPCP allows concurrent instruction execution by returning the null (CA= 0, IA = 1,
PF=0) primitive to the MPU.
2. The MPU encounters the next FPCP instruction and attempts to initiate execution by
writing to the command or condition CIR. The MPU then starts a read from the
response CiR to determine what further action should be taken.
3. The FPCP queues the instruction initiation request and changes the encoding of the
response CIR to null (CA-- 1, IA= 1), causing the MPU to wait.
4. The MPU continues to read the response CIR repeatedly until a new primitive is
encoded or an interrupt becomes pending (if an interrupt occurs, the MPU resumes
polling of the response CIR after the interrupt handler executes an RTE instruction).
5. The MC68881 APU becomes idle (by completing the previous instruction) and waits
for the next read of the response CIR. In the MC68882, the CU hands off the instruction
to the APU after the APU completes the previous instruction and waits for the next
read of the response CIR.
6. The MPU reads the response CIR, which either results in the return of a take exception
primitive (due to an exception during the previous instruction) or causes the FPCP to
begin execution of the new instruction by returning the first primitive required for
that operation.
The timing relationship of the main processor and the FPCP during this sequence can affect
the overall execution time of the new instruction, due to synchronization between the two
devices. Specifically, if the MPU begins a read of the response CIR exactly one clock cycle
before the FPCP completes the execution of the previous instruction in the APU, the FPCP
immediately begins execution of the new instruction by returning the first primitive of the
new instruction dialog during that read cycle. This case is shown in Figure 8-2, which
illustrates the best-case timing for coprocessor interface overhead: two clock cycles.
Figure 8-2 also illustrates the typical coprocessor interface overhead timing, which occurs
when the MPU initiates a new instruction and the FPCP is in the idle state. For this case,
there is no overlap with a previous instruction at the beginning of the instruction dialog,
and the coprocessor interface overhead for the new instruction is 11 clock cycles. Also,
MC68881/MC68882 USER'S MANUAL FREESCALE
8-7
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