The total number of clocks required for the bus activity in each entry can be derived by
multiplying the total number of bus cycles by three. (This does not account for the fact
that reads from the response and save CIRs require five clocks rather than three, but the
two clock-cycle discrepancy is usually negligible compared with the overall execution time
for an instruction.) For some instructions, the number of coprocessor read cycles indicated
by the tables may not reflect the actual number of read cycles that are executed during
the dialog for the instruction. This is because only the first occurrence of a series of null
(CA = 1, IA = 1) or null (CA = 0, PF = 0, IA = 1 ) primitives is included in the tables. For example,
the FPCP forces the main processor to wait during the conversion phase of the FMOVE
FPn,<ea> instruction by using the null response primitive. The MPU may perform nu-
merous response CIR read cycles during the time that it waits for the FPCP, but only the
first of this series of read cycles is included in the timing table entry. Although this Sim-
plification may fail to indicate the true number of coprocessor read cycles executed by the
MPU, it allows the tables to accurately indicate the minimum number of different response
primitive and operand reads that must be executed by a main processor, regardless of its
type or clock and bus speed.
The timing tables in the following paragraphs are divided into two major groups. First,
several tables are presented that allow quick determination of the typical execution time
for all instructions. These tables are comprehensive but assume typical operand inputs
and operating conditions for simplicity. No more than two tables are used to determine
the typical execution time for a given instruction. One table is used to determine the basic
execution time for the selected instruction, and a second table (one of five listing the
instruction groups) is used to determine the additional time required for the calculation of
the effective address by the MPU, for those instructions that require an effective address
calculation.
The second group of tables is used to calculate a more precise execution timing value for
a specific instruction, addressing mode, and operand type combination than is available
in the first group of tables. This group of tables is also useful for the calculation of execution
times where the main processor is not a MPU, since the timing for each phase of instruction
execution is included in a separate table. This alows timings that are only dependent on
the FPCP to be calculated and added to the timing characteristic of the main processor.
8.5.1 Timing Tables for Typical Execution
This set of tables allows a quick determination Of the typical execution time for any FPCP
instruction when the MPU is used as the main processor. The first table presented is for
effective address calculations performed by the MPU. Entries from this table are added to
the entries in the other tables in this subsection, if necessary, to obtain the overall execution
time for an operation. The assumptions that apply to the following tables are:
• The main processor is an MC68020 and operates on the same clock as the FPCP.
Instruction prefetches do not hit in the MC68020 cache (or it is disabled), and the
instruction is aligned so that a prefetch occurs before the command CIR is written by
the MC68020.
NOTE
The timing numbers are derived assuming that the main processor is an
MC68020. The MC68030 has a more optimized coprocessor interface and can
benefit from the data cache hits. These improvements of the coprocessor
interface are not used in determining typical operation. Actual operation
when using the MC68030 always yields better values than the calculations
derived from these tables.
MC68881/MC68882 USER'S MANUAL FREESCALE
8-11
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