8
A 32-bit memory interface is used, and memory accesses occur with zero wait states.
All memory operands, as well as the stack pointers, are long word aligned.
Accesses to the FPCP require three clock cycles, with the exception of read accesses
to the response and save CIRs, which require five clock cycles.
No instruction overlap is utilized so the coprocessor interface overhead is 11 clocks.
This can be reduced to two clock cycles if optimized code sequences are used or may
bell clock cycles if overlap is attempted and a synchronization delay is required.
Typical operand conversion and calculation times are used (i.e., input operands are
assumed to be normalized numbers in the legal range for a given function).
No exception is enabled, no exception occurs, and the default rounding mode and
precision of round-to-nearest, extended precision is used.
8.5.1.1 EFFECTIVE ADDRESS CALCULATIONS. For any instruction that requires an op-
erand external to the FPCP, an evaluate effective address and transfer data response pri-
mitive is issued by the FPCP during the dialog for that instruction. The amount of time
that is required for the MPU to calculate the effective address while processing this primitive
for each addressing mode, excluding the transfer of the data to the FPCP, is shown in Table
8-1. The times shown in this table include all bus cycles required to perform the address
calculation (such an instruction prefetches and memory indirect fetches).
For the FMOVEM instruction, Table 8-1 is also used to determine the time required for the
MPU to perform an address calculation (implied by the transfer multiple coprocessor reg-
isters primitive). For the FScc, FRESTORE, and FSAVE instructions, the request to evaluate
an effective address is implied by the F-line instruction word; therefore, no response
primitive is issued by the FPCP to request the evaluation. The following table is used for
these three instructions to adjust the basic instruction execution time to reflect the ad-
dressing mode that is used.
Note that Table 8-1 applies only to the MPU effective address calculation time for copro-
cessor instructions. The execution times included in this table are not the same as the
calculate effective address times given in the MPU user's manuals for normal instruction
execution.
8.5.1.2 ARITHMETIC OPERATIONS. Three tables provide the typical instruction execution
time for each arithmetic instruction. This group of instructions includes the majority of the
FPCP operations such as FADD, FSUB, etc. In addition to the instructions that perform
arithmetic calculations as part of their function, the FCMP, FMOVE, and FTST instructions
are also included since an implicit conversion is performed by those operations. For mem-
ory operands, the timing for the appropriate effective addressing mode must be added to
the numbers in these tables to determine the overall instruction execution times. In order
to simplify these tables, the overall execution times for the MC68881 are listed in Table 8-
2, the overall execution times for the MC68882 are listed in Table 8-3, and the bus cycle
activity numbers are listed in Table 8-4. In addition to the total execution times for the
MC68882, Table 8-3 lists the head and tail values required for calculating concurrency.
FREESCALE
8-12
MC68881/MC68882 USER'S MANUAL
To Next Page