Table of Figures
Figure 1: Key to logic diagrams 11
Figure 2: Functional Overview (P24DM) 12
Figure 3: Hardware design overview 30
Figure 4: Exploded view of IED 32
Figure 5: 20TE rear panel 33
Figure 6: 30TE Three-MIDOS block rear panel 34
Figure 7: 30TE Two-MIDOS block + communications rear panel 34
Figure 8: 30TE Two-MIDOS block + blanking plate 35
Figure 9: 40TE Three-MIDOS block + communications rear panel 35
Figure 10: Front panel (20TE) 37
Figure 11: Front panel (30TE) 38
Figure 12: Front panel (40TE) 39
Figure 13: Software structure 46
Figure 14: Frequency Response (indicative only) 51
Figure 15: Navigating the HMI 58
Figure 16: Default display navigation 60
Figure 17: Thermal overload protection logic diagram 77
Figure 18: Cooling time constant 77
Figure 19: Example of settings 80
Figure 20: Thermal curve modification 82
Figure 21: IEC 60255 IDMT curves 87
Figure 22: IEC standard and very inverse curves 90
Figure 23: IEC Extremely inverse and IEEE moderate inverse curves 90
Figure 24: IEEE very and extremely inverse curves 91
Figure 25: Principle of protection function implementation 92
Figure 26: Non-directional Overcurrent Logic diagram 95
Figure 27: Directional trip angles 97
Figure 28: Directional Overcurrent Logic diagram (Phase A shown only) 98
Figure 29: OR logic 99
Figure 30: AND logic 99
Figure 31: Definite time overcurrent element 100
Figure 32: Selecting the current threshold setting 101
Figure 33: Negative Sequence Overcurrent logic - non-directional operation 103
Figure 34: Negative Sequence Overcurrent logic - directional operation 104
Figure 35: Equivalent circuits 105
Figure 36: IDG Characteristic 111
Figure 37: Directional angles 112
Figure 38: Directional EF logic with neutral voltage polarization (single stage) 113
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