GE P24DM - Positive Sequence Undervoltage Protection; Positive Sequence Undervoltage Implementation; Positive Sequence Undervoltage Logic; Figure 104: Positive Sequence Undervoltage Logic

6 POSITIVE SEQUENCE UNDERVOLTAGE PROTECTION
6.1 POSITIVE SEQUENCE UNDERVOLTAGE IMPLEMENTATION
Positive Sequence Undervoltage Protection is implemented under the P
OS SEQ U/V heading in the VOLT
PROTECTION Voltage column of the relevant settings group.
The product provides two stages of Positive Sequence Undervoltage protection with independent time delay
characteristics.
Stage 1 provides a choice of operate characteristics, where you can select between:
● An IDMT characteristic
● DT (Definite Time)
You set this using the V1<1 Function cell.
The IDMT characteristic is defined by the following formula:
t = K/( M-1)
where:
● K = Time multiplier setting
● t = Operating time in seconds
● M = Measured voltage / IED setting voltage
There is no Timer Hold facility for Undervoltage.
Stage 2 can have definite time characteristics only. This is set in the V1<2 status cell.
Two stages are included in order to provide multiple output types, such as alarm and trip stages.
6.2 POSITIVE SEQUENCE UNDERVOLTAGE LOGIC
V00816
V1
V1<1 Voltage Set
&
V1<1 Time Delay
V1<1 Trip
V1<1 Start
&
V1<1 Timer Block
V<1 Poledead Inh
Enabled
All Poles Dead
&
Note: This diagram does not show all stages . Other stages follow similar principles.
VTS Fast Block only applies for directional models .
VTS Fast Block
&
VTS Block 1
Enabled
Figure 104: Positive Sequence Undervoltage logic
Chapter 10 - Voltage Protection Functions P24xM
216 P24xM-TM-EN-2.1