GE P24DM - Figure 1: Key to Logic Diagrams

V00063
Key:
DDB Signal
Internal function
&AND gate
OR gate
1
Setting cell
Setting value Timer
SR Latch
Reset Dominant
Internal Signal
0Logic 0
Comparator for detecting
overvalues
Energising Quantity
Hardcoded setting
R
D
Q
S
Comparator for detecting
undervalues
Switch
Measurement Cell
Derived setting
SR Latch
HMI key
Pulse / Latch
Connection / Node Inverted logic input
Soft switch
Latched on positive edge
XMultiplier
2
1
NOT gate
XOR
XOR gate
R
Q
S
Internal Calculation
Switch
Bandpass filter
Figure 1: Key to logic diagrams
P24xM Chapter 1 - Introduction
P24xM-TM-EN-2.1 11