GE P24DM - Chapter Overview

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1 CHAPTER OVERVIEW

The device provides a Circuit Breaker Fail Protection function. This chapter describes the operation of this function

including the principles, logic diagrams and applications.

This chapter contains the following sections:

Chapter Overview 179

Cir

cuit Breaker Fail Protection 180

Circuit Breaker Fail Implementation 181

Circuit Breaker Fail Logic 183

Undercurrent and ZCD Logic for CB Fail 185

CB Fail SEF Protection Logic 186

CB Fail Non Current Protection Logic 187

Circuit Breaker Mapping 188

Application Notes 189

P24xM Chapter 8 - CB Fail Protection

P24xM-TM-EN-2.1 179

Main Page

default chapter3
- Table of Contents3
Chapter 1 Introduction25
- Figure 135: TCS Scheme25
- Rear Serial Port26
- Figure 137: TCS Scheme26
- Chapter Overview27
- Cip27
- Foreword28
- Target Audience28
- Typographical Conventions28
- Cip28
- Figure 142: PSL for TCS Scheme28
- Nomenclature29
- Compliance29
- Cip29
- Product Scope30
- Ordering Options30
- Cip30
- Features and Functions31
- Protection Functions31
- Control Functions32
- Measurement Functions32
- Communication Functions33
- Logic Diagrams34
- Figure 1: Key to Logic Diagrams35
- Functional Overview36
- Figure 2: Functional Overview (P24DM)36
Chapter 2 Safety Information37
- Chapter Overview39
- Health and Safety40
- Symbols41
- Installation, Commissioning and Servicing42
- Lifting Hazards42
- Electrical Hazards42
- UL/CSA/CUL Requirements43
- Fusing Requirements43
- Equipment Connections44
- Protection Class 1 Equipment Requirements44
- Pre-Energisation Checklist45
- Peripheral Circuitry45
- Upgrading/Servicing47
- Decommissioning and Disposal48
- Regulatory Compliance49
- EMC Compliance: 2014/30/EU49
- LVD Compliance: 2014/35/EU49
- R&TTE Compliance: 2014/53/EU49
- UL/CUL Compliance49
- ATEX Compliance: 2014/34/EU49
Chapter 3 Hardware Design51
- Chapter Overview53
- Hardware Architecture54
- Memory and Real Time Clock54
- Figure 3: Hardware Design Overview54
- Mechanical Implementation56
- Housing Variants56
- Figure 4: Exploded View of IED56
- 20TE Rear Panel57
- Figure 5: 20TE Rear Panel57
- Figure 6: 30TE Three-MIDOS Block Rear Panel58
- Figure 7: 30TE Two-MIDOS Block + Communications Rear Panel58
- 40TE Rear Panel59
- Figure 8: 30TE Two-MIDOS Block + Blanking Plate59
- Figure 9: 40TE Three-MIDOS Block + Communications Rear Panel59
- Terminal Connections60
- I/O Options60
- Front Panel61
- 20TE Front Panel61
- Figure 10: Front Panel (20TE)61
- 30TE Front Panel62
- Figure 11: Front Panel (30TE)62
- 40TE Front Panel63
- Keypad63
- Figure 12: Front Panel (40TE)63
- Liquid Crystal Display64
- USB Port64
- Fixed Function Leds65
- Function Keys65
- Programable Leds65
Chapter 4 Software Design67
- Chapter Overview69
- Software Design Overview70
- Figure 13: Software Structure70
- System Level Software71
- Real Time Operating System71
- System Services Software71
- Self-Diagnostic Software71
- Startup Self-Testing71
- System Boot71
- System Level Software Initialisation72
- Platform Software Initialisation and Monitoring72
- Continuous Self-Testing72
- Platform Software73
- Record Logging73
- Settings Database73
- Interfaces73
- Protection and Control Functions74
- Acquisition of Samples74
- Frequency Tracking74
- Fourier Signal Processing74
- Programmable Scheme Logic75
- Event Recording75
- Figure 14: Frequency Response (Indicative Only)75
- Disturbance Recorder76
- Function Key Interface76
Chapter 5 Configuration77
- Chapter Overview79
- Settings Application Software80
- Using the HMI Panel81
- Navigating the HMI Panel82
- Getting Started82
- Figure 15: Navigating the HMI82
- Default Display83
- Default Display Navigation84
- Figure 16: Default Display Navigation84
- Password Entry85
- Processing Alarms and Records86
- Menu Structure86
- Changing the Settings87
- Direct Access (the Hotkey Menu)88
- Setting Group Selection Using Hotkeys88
- Control Inputs89
- Circuit Breaker Control89
- Function Keys90
- Date and Time Configuration92
- Time Zone Compensation92
- Daylight Saving Time Compensation92
- Settings Group Selection93
Chapter 6 Current Protection Functions95
- Chapter Overview97
- Thermal Overload Protection98
- Thermal Replica99
- Thermal Trip100
- Figure 17: Thermal Overload Protection Logic Diagram101
- Figure 18: Cooling Time Constant101
- User Programmable Curve for Thermal Overload Protection102
- Application Notes102
- Thermal Overload Setting Guidelines102
- Figure 19: Example of Settings104
- Figure 20: Thermal Curve Modification106
- Overcurrent Protection Principles108
- IDMT Characteristics108
- IEC 60255 IDMT Curves109
- European Standards111
- Figure 21: IEC 60255 IDMT Curves111
- North American Standards112
- IEC and IEEE Inverse Curves114
- Figure 22: IEC Standard and very Inverse Curves114
- Figure 23: IEC Extremely Inverse and IEEE Moderate Inverse Curves114
- Differences between the North American and European Standards115
- Programmable Curves115
- Principles of Implementation115
- Figure 24: IEEE very and Extremely Inverse Curves115
- Timer Hold Facility116
- Figure 25: Principle of Protection Function Implementation116
- Phase Overcurrent Protection118
- Phase Overcurrent Protection Implementation118
- Non-Directional Overcurrent Logic119
- Figure 26: Non-Directional Overcurrent Logic Diagram119
- Directional Element120
- Figure 27: Directional Trip Angles121
- Directional Overcurrent Logic122
- Application Notes122
- Short Circuit Protection122
- Figure 28: Directional Overcurrent Logic Diagram (Phase a Shown Only)122
- Figure 29: or Logic123
- Figure 30: and Logic123
- Figure 31: Definite Time Overcurrent Element124
- Current Setting Threshold Selection125
- Figure 32: Selecting the Current Threshold Setting125
- Negative Sequence Overcurrent Protection126
- Negative Sequence Overcurrent Protection Implementation126
- Non-Directional Negative Sequence Overcurrent Logic127
- Directional Element127
- Figure 33: Negative Sequence Overcurrent Logic - Non-Directional Operation127
- Directional Negative Sequence Overcurrent Logic128
- Phase Rotation128
- Figure 34: Negative Sequence Overcurrent Logic - Directional Operation128
- Application Notes129
- Negative Sequence Protection129
- Figure 35: Equivalent Circuits129
- Earth Fault Protection133
- Earth Fault Protection Elements133
- Non-Directional Earth Fault Logic134
- IDG Curve134
- Directional Element135
- Residual Voltage Polarisation135
- Figure 36: IDG Characteristic135
- Figure 37: Directional Angles136
- Negative Sequence Polarisation137
- Figure 38: Directional EF Logic with Neutral Voltage Polarization (Single Stage)137
- Application Notes138
- Setting Guidelines (Directional Element)138
- Figure 39: Directional Angles138
- Figure 40: *Directional Earth Fault Logic with Negative Sequence Polarisation (Single Stage)138
- Peterson Coil Earthed Systems139
- Figure 41: Current Level (Amps) at Which Transient Faults Are Self-Extinguishing139
- Figure 42: Earth Fault in Petersen Coil Earthed System140
- Figure 43: Distribution of Currents During a Phase C Fault140
- Figure 44: Phasors for a Phase C Earth Fault in a Petersen Coil Earthed System141
- Figure 45: Zero Sequence Network Showing Residual Currents141
- Setting Guidelines (Compensated Networks)142
- Figure 46: Phase C Earth Fault in Petersen Coil Earthed System: Practical Case with Resistance142
- Solidly Earthed System143
- Insulated System144
- Figure 47: Fuse Characteristic144
- Figure 48: Current Distribution in an Insulated System with C Phase Fault145
- Figure 49: Phasor Diagrams for Insulated System with C Phase Fault146
- Resistance Earthed Systems147
- High Resistance Earthing147
- Petersen Coil Earthed Systems148
- Figure 50: Directional Tripping Characteristic148
- Figure 51: Current Distribution in Petersen Coil Earthed System149
- Figure 52: Distribution of Currents During a C Phase to Earth Fault150
- Figure 53: Theoretical Case - no Resistance Present in XL or XC150
- Figure 54: Zero Sequence Network Showing Residual Currents151
- Figure 55: Practical Case:- Resistance Present in XL and XC152
- Operation of Sensitive Earth Fault Element153
- Sensitive Earth Fault Protection154
- SEF Protection Implementation154
- Non-Directional SEF Logic154
- Figure 56: Non-Directional SEF Logic154
- EPATR B Curve155
- Directional Element155
- Figure 57: EPATR B Characteristic Shown for TMS = 1.0155
- Wattmetric Characteristic156
- Figure 58: Resistive Components of Spill Current156
- Icos Phi / Isin Phi Characteristic157
- Figure 59: Operating Characteristic for Icos157
- Directional SEF Logic158
- Figure 60: Directional SEF with VN Polarisation (Single Stage)158
- Application Notes159
- Insulated Systems159
- Figure 61: Current Distribution in an Insulated System with C Phase Fault159
- Setting Guidelines (Insulated Systems)160
- Figure 62: Phasor Diagrams for Insulated System with C Phase Fault160
- Figure 63: Positioning of Core Balance Current Transformers161
- Cold Load Pickup162
- Implementation162
- CLP Logic163
- Application Notes163
- CLP for Resistive Loads163
- CLP for Motor Feeders163
- Figure 64: Cold Load Pickup Logic163
- CLP for Switch Onto Fault Conditions164
- Selective Logic165
- Selective Logic Implementation165
- Selective Logic Diagram165
- Figure 65: Selective Logic165
- Timer Setting Selection166
- Figure 66: Selecting the Timer Settings166
- Blocked Overcurrent Protection167
- Blocked Overcurrent Implementation167
- Blocked Overcurrent Logic167
- Blocked Earth Fault Logic167
- Figure 67: Blocked Overcurrent Logic167
- Application Notes168
- Busbar Blocking Scheme168
- Figure 68: Blocked Earth Fault Logic168
- Figure 69: Simple Busbar Blocking Scheme168
- Figure 70: Simple Busbar Blocking Scheme Characteristics169
- Second Harmonic Blocking170
- Second Harmonic Blocking Implementation170
- Second Harmonic Blocking Logic (POC Input)171
- Application Notes171
- Setting Guidelines171
- Figure 71: 2Nd Harmonic Blocking Logic (POC Input)171
- Stall Protection172
- Prolonged Start172
- Figure 72: Start Successful172
- Locked Rotor During Starting - (Stall Time < Start Time)173
- Figure 73: Locked Rotor Detection173
- Stall During Running174
- Momentary Reduction in System Voltage During Running174
- Reacceleration after a Reduction in System Voltage174
- Figure 74: Reacceleration Detection174
- Low Voltage Ride through Authorization175
- Figure 75: Adjustable Reacceleration Authorization - Voltage Restored Within the Set Time175
- Auto Re-Start Authorization Restoration Sequence176
- Figure 76: Adjustable Reacceleration Authorization - Voltage Restored after the Set Time176
- Figure 77: Automatic Restart Authorized- Voltage Restored Within the Set Time177
- Application Notes178
- Start/Stall Protection178
- Figure 78: Automatic Restart Failed- Voltage Restored after the Set Time178
- Excessive Start Time/Locked Rotor Protection - Stall Time > Start Time179
- Stall Protection (Stall While Running)179
- Excessive Start Time/Locked Rotor Protection - Stall Time < Start Time180
- Momentary Reduction in System Voltage During Running of the Motor180
- Low Voltage Protection (Reacceleration Authorization)181
- AUTO RE-START Authorization181
- Number of Starts182
- Figure 79: Start Inhibition Example 1183
- Time between Starts184
- Figure 80: Start Inhibition Example 2184
- Number of Starts Limitation185
- Figure 81: Time between Starts185
- Anti-Backspin Protection186
- Application Notes187
- Anti-Backspin Protection187
Chapter 7 Restricted Earth Fault Protection189
- Chapter Overview191
- REF Protection Principles192
- Figure 83: REF Protection for Delta Connected Winding192
- Figure 84: REF Protection for Star Connected Winding192
- Restricted Earth Fault Types193
- Low Impedance Bias Characteristic193
- High Impedance REF Principle194
- Figure 85: Three-Slope REF Bias Characteristic194
- Figure 86: High Impedance REF Principle194
- Figure 87: High Impedance REF Connection195
- Restricted Earth Fault Protection Implementation196
- Restricted Earth Fault Protection Settings196
- Low Impedance REF196
- Setting the Bias Characteristic196
- Figure 88: REF Bias Characteristic196
- Delayed Bias197
- High Impedance REF197
- High Impedance REF Calculation Principles197
- Application Notes199
- Low Impedance REF Protection Application199
- Setting Guidelines for Biased Operation199
- Low Impedance REF Scaling Factor199
- Figure 89: Low Impedance REF Scaling Factor199
- High Impedance REF Protection Application200
- Setting Guidelines for High Impedance Operation200
Chapter 8 CB Fail Protection201
- Chapter Overview203
- Circuit Breaker Fail Protection204
- Circuit Breaker Fail Implementation205
- Circuit Breaker Fail Timers205
- Zero Crossing Detection205
- Circuit Breaker Fail Logic207
- Figure 90: Circuit Breaker Fail Logic - Three Phase Start207
- Figure 91: Circuit Breaker Fail Logic - Single Phase Start208
- Figure 92: Circuit Breaker Fail Trip and Alarm208
- Undercurrent and ZCD Logic for CB Fail209
- Figure 93: Undercurrent and Zero Crossing Detection Logic for CB Fail209
- CB Fail SEF Protection Logic210
- Figure 94: CB Fail SEF Protection Logic210
- CB Fail Non Current Protection Logic211
- Figure 95: CB Fail Non Current Protection Logic211
- Circuit Breaker Mapping212
- Figure 96: Circuit Breaker Mapping212
- Application Notes213
- Reset Mechanisms for CB Fail Timers213
- Setting Guidelines (CB Fail Timer)213
- Setting Guidelines (Undercurrent)214
- Figure 97: CB Fail Timing214
Chapter 9 Current Transformer Requirements215
- Chapter Overview217
- CT Requirements218
- Phase Overcurrent Protection218
- Directional Elements218
- Non-Directional Elements219
- Earth Fault Protection219
- Directional Elements219
- SEF Protection (Residually Connected)219
- Non-Directional Elements220
- SEF Protection (Core-Balanced CT)220
- Low Impedance REF Protection220
- High Impedance REF Protection221
- Use of Metrosil Non-Linear Resistors221
- Use of ANSI C-Class Cts223
Chapter 10 Voltage Protection Functions225
- Chapter Overview227
- Undervoltage Protection228
- Undervoltage Protection Implementation228
- Undervoltage Protection Logic229
- Figure 98: Undervoltage - Single and Three Phase Tripping Mode (Single Stage)229
- Application Notes230
- Undervoltage Protection230
- Overvoltage Protection231
- Overvoltage Protection Implementation231
- Overvoltage Protection Logic232
- Figure 99: Overvoltage - Single and Three Phase Tripping Mode (Single Stage)232
- Application Notes233
- Overvoltage Setting Guidelines233
- Residual Overvoltage Protection234
- Residual Overvoltage Protection Implementation234
- Residual Overvoltage Logic235
- Application Notes235
- Calculation for Solidly Earthed Systems235
- Figure 100: Residual Overvoltage Logic235
- Calculation for Impedance Earthed Systems236
- Figure 101: Residual Voltage for a Solidly Earthed System236
- Setting Guidelines237
- Figure 102: Residual Voltage for an Impedance Earthed System237
- Negative Sequence Overvoltage Protection238
- Negative Sequence Overvoltage Implementation238
- Negative Sequence Overvoltage Logic238
- Application Notes238
- Setting Guidelines238
- Figure 103: Negative Sequence Overvoltage Logic238
- Positive Sequence Undervoltage Protection240
- Positive Sequence Undervoltage Implementation240
- Positive Sequence Undervoltage Logic240
- Figure 104: Positive Sequence Undervoltage Logic240
- Positive Sequence Overvoltage Protection241
- Positive Sequence Overvoltage Implementation241
- Positive Sequence Overvoltage Logic241
- Figure 105: Positive Sequence Overvoltage Logic241
- Moving Average Voltage Functions242
- Moving Average Undervoltage Logic242
- Figure 106: Moving Average Undervoltage Logic242
- Moving Average Overvoltage Logic243
- Moving Average Zero Sequence Voltage Logic243
- Figure 107: Moving Average Overvoltage Logic243
- Figure 108: Moving Average Zero Sequence Voltage Logic243
- Moving Average Positive Sequence Voltage Logic244
- Moving Average Negative Sequence Voltage Logic244
- Moving Average Undervoltage Blocking PSL244
- Figure 109: Moving Average Positive Sequence Voltage Logic244
- Figure 110: Moving Average Negative Sequence Voltage Logic244
- Figure 111: Average Voltage Protection Blocking244
Chapter 11 Frequency Protection Functions245
- Chapter Overview247
- Frequency Protection Overview248
- Frequency Protection Implementation248
- Underfrequency Protection249
- Underfrequency Protection Implementation249
- Underfrequency Protection Logic249
- Application Notes249
- Setting Guidelines249
- Figure 112: Underfrequency Logic (Single Stage)249
- Overfrequency Protection251
- Overfrequency Protection Implementation251
- Overfrequency Protection Logic251
- Application Notes251
- Setting Guidelines251
- Figure 113: Overfrequency Logic (Single Stage)251
- Figure 114: Power System Segregation Based Upon Frequency Measurements252
- Independent R.O.C.O.F Protection253
- Indepenent R.O.C.O.F Protection Implementation253
- Independent R.O.C.O.F Protection Logic253
- Figure 115: Independent Rate of Change of Frequency Logic (Single Stage)253
- Application Notes254
- Setting Guidelines254
- Frequency-Supervised R.O.C.O.F Protection255
- Frequency-Supervised R.O.C.O.F Implementation255
- Frequency-Supervised R.O.C.O.F Logic256
- Application Notes256
- Frequency-Supervised R.O.C.O.F Example256
- Figure 116: Frequency-Supervised Rate of Change of Frequency Logic (Single Stage)256
- Setting Guidelines257
- Figure 117: Frequency Supervised Rate of Change of Frequency Protection257
- Average Rate of Change of Frequency Protection258
- Average R.O.C.O.F Protection Implementation258
- Figure 118: Average Rate of Change of Frequency Characteristic258
- Average R.O.C.O.F Logic259
- Application Notes259
- Setting Guidelines259
- Figure 119: Average Rate of Change of Frequency Logic (Single Stage)259
Chapter 12 Power Protection Functions261
- Chapter Overview263
- Reverse Power Protection264
- Reverse Power Implementation264
Chapter 13 Monitoring and Control265
- Chapter Overview267
- Event Records268
- Event Types268
- Opto-Input Events269
- Contact Events269
- Alarm Events269
- Fault Record Events274
- Security Events274
- Figure 120: Fault Recorder Stop Conditions274
- Maintenance Events275
- Protection Events275
- Platform Events275
- Disturbance Recorder276
- Measurements277
- Measured Quantities277
- Measured and Calculated Currents277
- Measured and Calculated Voltages277
- Power and Energy Quantities277
- Demand Values278
- Frequency Measurements278
- Other Measurements278
- Measurement Setup278
- Opto-Input Time Stamping279
- CB Condition Monitoring280
- Application Notes280
- Setting the Thresholds for the Total Broken Current280
- Setting the Thresholds for the Number of Operations280
- Setting the Thresholds for the Operating Time281
- Setting the Thresholds for Excesssive Fault Frequency281
- CB State Monitoring282
- CB State Monitoring Logic283
- Figure 121: CB State Monitoring Logic283
- Circuit Breaker Control284
- CB Control Using the IED Menu284
- CB Control Using the Hotkeys285
- CB Control Using the Function Keys285
- Figure 122: Hotkey Menu Navigation285
- CB Control Using the Opto-Inputs286
- Remote CB Control286
- Figure 123: Default Function Key PSL286
- CB Healthy Check287
- Figure 124: Remote Control of Circuit Breaker287
- CB Control Logic288
- Figure 125: CB Control Logic288
- Pole Dead Function289
- Pole Dead Logic289
- Figure 126: Pole Dead Logic289
- System Checks290
- System Checks Implementation290
- VT Connections290
- Voltage Monitoring290
- Switch Status and Control291
- Figure 127: Representation of Typical Feeder Bay291
- Switch Status Logic292
- Figure 128: Switch Status Logic292
- Switch Control Logic293
- Figure 129: Switch Control Logic293
Chapter 14 Supervision295
- Chapter Overview297
- DC Supply Monitor298
- DC Supply Monitor Implementation298
- Figure 130: DC Supply Monitor Zones298
- DC Supply Monitor Logic299
- Figure 131: DC Supply Monitor Logic299
- Voltage Transformer Supervision300
- Loss of One or Two Phase Voltages300
- Loss of All Three Phase Voltages300
- Absence of All Three Phase Voltages on Line Energisation300
- VTS Implementation301
- VTS Logic301
- Figure 132: VTS Logic302
- VTS Acceleration Indication Logic303
- Figure 133: VTS Acceleration Indication Logic303
- Current Transformer Supervision304
- CTS Implementation304
- CTS Logic304
- Figure 134: CTS Logic Diagram304
- Application Notes305
- Setting Guidelines305
- Trip Circuit Supervision306
- Trip Circuit Supervision Scheme306
- Resistor Values306
- Psl for Tcs Scheme 1307
- Trip Circuit Supervision Scheme307
- Resistor Values308
- Psl for Tcs Scheme 2308
- Trip Circuit Supervision Scheme 3309
- Resistor Values309
- Figure 139: TCS Scheme 3309
- Psl for Tcs Scheme 3310
- Trip Circuit Supervision Scheme310
- Figure 140310
- Figure 141: TCS Scheme 4310
- Resistor Values311
- Figure 136: PSL for TCS Scheme311
- Figure 138: PSL for TCS Scheme311
Chapter 15 Digital I/O and PSL Configuration313
- Chapter Overview315
- Configuring Digital Inputs and Outputs316
- Scheme Logic317
- Figure 143: Scheme Logic Interfaces317
- PSL Editor318
- PSL Schemes318
- PSL Scheme Version Control318
- Configuring the Opto-Inputs319
- Assigning the Output Relays320
- Fixed Function Leds321
- Trip LED Logic321
- Figure 144: Trip LED Logic321
- Configuring Programmable Leds322
- Function Keys324
- Control Inputs325
- Inter-PSL Inputs and Outputs326
Chapter 16 Communications327
- Chapter Overview329
- Communication Interfaces330
- Serial Communication331
- Universal Serial Bus331
- EIA(RS)485 Bus331
- EIA(RS)485 Biasing Requirements332
- K-Bus332
- Figure 145: RS485 Biasing Circuit332
- Figure 146: Remote Communication Using K-Bus333
- Standard Ethernet Communication334
- Redundant Ethernet Communication335
- Supported Protocols335
- Parallel Redundancy Protocol335
- High-Availability Seamless Redundancy (HSR)336
- HSR Multicast Topology336
- Figure 147: IED Attached to Separate Lans336
- HSR Unicast Topology337
- Figure 148: HSR Multicast Topology337
- HSR Application in the Substation338
- Figure 149: HSR Unicast Topology338
- Rapid Spanning Tree Protocol339
- Figure 150: HSR Application in the Substation339
- Figure 151: IED Attached to Redundant Ethernet Star or Ring Circuit339
- Configuring IP Address340
- Data Protocols341
- Courier341
- Physical Connection and Link Layer341
- Courier Database341
- Settings Categories342
- Setting Changes342
- Event Extraction342
- Disturbance Record Extraction344
- Programmable Scheme Logic Settings344
- Time Synchronisation344
- Courier Configuration344
- Physical Connection and Link Layer346
- Initialisation347
- Time Synchronisation347
- Spontaneous Events347
- General Interrogation (GI)347
- Cyclic Measurements347
- Commands347
- Test Mode347
- Disturbance Records348
- Command/Monitor Blocking348
- IEC 60870-5-103 Configuration348
- Dnp349
- Physical Connection and Link Layer349
- Object 1 Binary Inputs350
- Object 10 Binary Outputs350
- Figure 152: Control Input Behaviour350
- Object 20 Binary Counters351
- Object 30 Analogue Input351
- Object 40 Analogue Output351
- Object 50 Time Synchronisation351
- DNP3 Device Profile352
- DNP3 Configuration360
- DNP3 Unsolicited Reporting361
- Modbus361
- Physical Connection and Link Layer361
- MODBUS Functions361
- Response Codes362
- Register Mapping362
- Event Extraction363
- Disturbance Record Extraction364
- Figure 153: Manual Selection of a Disturbance Record366
- Figure 154: Automatic Selection of Disturbance Record - Method 1367
- Figure 155: Automatic Selection of Disturbance Record - Method 2368
- Figure 156: Configuration File Extraction369
- Figure 157: Data File Extraction370
- Setting Changes371
- Password Protection371
- Protection and Disturbance Recorder Settings371
- Time Synchronisation372
- Power and Energy Measurement Data Formats373
- MODBUS Configuration374
- Iec 61850375
- Benefits of IEC 61850375
- IEC 61850 Interoperability376
- The IEC 61850 Data Model376
- Figure 158: Data Model Layers in IEC61850376
- IEC 61850 in Micom Ieds377
- IEC 61850 Data Model Implementation377
- IEC 61850 Communication Services Implementation377
- IEC 61850 Peer-To-Peer (GOOSE) Communications378
- Mapping GOOSE Messages to Virtual Inputs378
- Ethernet Functionality378
- IEC 61850 Configuration379
- Concurrent IEC 61850 and DNP3.0 Operation380
- Read Only Mode382
- Courier Protocol Blocking382
- IEC 61850 Protocol Blocking383
- Read-Only Settings383
- Read-Only DDB Signals383
- Time Synchronisation384
- Demodulated IRIG-B384
- Figure 159: GPS Satellite Timing Signal384
- Demodulated IRIG-B Implementation385
- Sntp385
- Time Synchronsiation Using the Communication Protocols385
Chapter 17 Cyber-Security387
- Overview389
- The Need for Cyber-Security390
- Standards391
- NERC Compliance391
- Cip 002392
- Cip 007393
- Ieee 1686-2007393
- Cyber-Security Implementation395
- NERC-Compliant Display395
- Four-Level Access396
- Figure 160: Default Display Navigation396
- Blank Passwords397
- Password Rules398
- Access Level Ddbs398
- Enhanced Password Security398
- Password Strengthening398
- Password Validation399
- Password Blocking399
- Password Recovery400
- Entry of the Recovery Password400
- Password Encryption401
- Disabling Physical Ports401
- Disabling Logical Ports401
- Security Events Management402
- Logging out404
Chapter 18 Installation405
- Chapter Overview407
- Handling the Goods408
- Receipt of the Goods408
- Unpacking the Goods408
- Storing the Goods408
- Dismantling the Goods408
- Mounting the Device409
- Flush Panel Mounting409
- Rack Mounting409
- Software Only410
- Figure 161: Rack Mounting of Products410
- Cables and Connectors412
- Terminal Blocks412
- Power Supply Connections412
- Figure 162: Midos Terminal Block412
- Earth Connnection413
- Current Transformers413
- Voltage Transformer Connections413
- Watchdog Connections414
- EIA(RS)485 and K-Bus Connections414
- IRIG-B Connection414
- Figure 163: Earth Link for Cable Screen414
- Opto-Input Connections415
- Output Relay Connections415
- Ethernet Metallic Connections415
- Ethernet Fibre Connections415
- USB Connection415
- Case Dimensions416
- Figure 164: 20TE Case Dimensions416
- Figure 165: 30TE Case Dimensions417
- Figure 166: 40TE Case Dimensions418
Chapter 19 Commissioning Instructions419
- Chapter Overview421
- General Guidelines422
- Commissioning Test Menu423
- Opto I/P Status Cell (Opto-Input Status)423
- Relay O/P Status Cell (Relay Output Status)423
- Test Port Status Cell423
- Monitor Bit 1 to 8 Cells423
- Test Mode Cell423
- Test Pattern Cell424
- Contact Test Cell424
- Test Leds Cell424
- Test Autoreclose Cell424
- Red and Green LED Status Cells424
- Commissioning Equipment426
- Recommended Commissioning Equipment426
- Essential Commissioning Equipment426
- Advisory Test Equipment427
- Product Checks428
- Product Checks with the IED De-Energised428
- Visual Inspection428
- Insulation429
- External Wiring429
- Watchdog Contacts429
- Power Supply429
- Product Checks with the IED Energised429
- Watchdog Contacts430
- Test LCD430
- Date and Time430
- Test Leds430
- Test Alarm and Out-Of-Service Leds431
- Test Trip LED431
- Test User-Programmable Leds431
- Test Opto-Inputs431
- Test Output Relays431
- Test Serial Communication Port RP1431
- Figure 167: RP1 Physical Connection432
- Test Serial Communication Port RP2433
- Test Ethernet Communication433
- Test Current Inputs433
- Figure 168: Remote Communication Using K-Bus433
- Test Voltage Inputs434
- Setting Checks436
- Apply Application-Specific Settings436
- Transferring Settings from a Settings File436
- Entering Settings Using the HMI436
- Protection Timing Checks438
- Overcurrent Check438
- Connecting the Test Circuit438
- Performing the Test438
- Check the Operating Time438
- Onload Checks440
- Confirm Current Connections440
- Confirm Voltage Connections440
- On-Load Directional Test441
- Final Checks442
Chapter 20 Maintenance and Troubleshooting443
- Chapter Overview445
- Maintenance446
- Maintenance Checks446
- Alarms446
- Opto-Isolators446
- Output Relays446
- Measurement Accuracy446
- Replacing the Unit447
- Cleaning447
- Troubleshooting448
- Self-Diagnostic Software448
- Power-Up Errors448
- Error Message or Code on Power-Up448
- Out of Service LED on at Power-Up449
- Error Code During Operation449
- Mal-Operation During Testing450
- Failure of Output Contacts450
- Failure of Opto-Inputs450
- Incorrect Analogue Signals450
- PSL Editor Troubleshooting450
- Diagram Reconstruction451
- PSL Version Check451
- Repair and Modification Procedure451
Chapter 21 Technical Specifications453
- Chapter Overview455
- Interfaces456
- Front USB Port456
- Rear Serial Port 1456
- IRIG-B Port456
- Rear Ethernet Port Copper457
- Rear Ethernet Port - Fibre457
- 100 Base Fx Receiver Characteristics457
- 100 Base Fx Transmitter Characteristics457
- Performance of Current Protection Functions458
- Three-Phase Overcurrent Protection458
- Three-Phase Overcurrent Directional Parameters458
- Thermal Overload Protection458
- Earth Fault Protection458
- Earth Fault Directional Parameters459
- Sensitive Earth Fault Protection459
- SEF Directional Parameters460
- Restricted Earth Fault Protection460
- Negative Sequence Overcurrent Protection460
- NPSOC Directional Parameters461
- Stall Protection461
- Circuit Breaker Fail and Undercurrent Protection461
- Broken Conductor Protection461
- Selective Overcurrent Protection461
- Cold Load Pickup Protection462
- Performance of Voltage Protection Functions463
- Undervoltage Protection463
- Overvoltage Protection463
- Residual Overvoltage Protection463
- Negative Sequence Voltage Protection463
- Rate of Change of Voltage Protection464
- Performance of Frequency Protection Functions465
- Overfrequency Protection465
- Underfrequency Protection465
- Supervised Rate of Change of Frequency Protection465
- Independent Rate of Change of Frequency Protection466
- Average Rate of Change of Frequency Protection466
- Load Restoration467
- Anti-Backspin467
- Power Protection Functions468
- Reverse Power Protection468
- Performance of Monitoring and Control Functions469
- Voltage Transformer Supervision469
- Current Transformer Supervision469
- CB State and Condition Monitoring469
- PSL Timers469
- DC Supply Monitor469
- Measurements and Recording471
- General471
- Measured Operating Data471
- Disturbance Records472
- Event, Fault and Maintenance Records472
- Regulatory Compliance473
- EMC Compliance: 2014/30/EU473
- LVD Compliance: 2014/35/EU473
- R&TTE Compliance: 2014/53/EU473
- UL/CUL Compliance473
- ATEX Compliance: 2014/34/EU473
- Mechanical Specifications475
- Physical Parameters475
- Enclosure Protection475
- Mechanical Robustness475
- Transit Packaging Performance475
- Ratings476
- AC Measuring Inputs476
- Current Transformer Inputs476
- Voltage Transformer Inputs476
- Power Supply477
- Auxiliary Power Supply Voltage477
- Nominal Burden477
- Auxiliary Power Supply Interruption477
- Input / Output Connections478
- Isolated Digital Inputs478
- Nominal Pickup and Reset Thresholds478
- Standard Output Contacts478
- Watchdog Contacts479
- Shorting Link479
- Environmental Conditions480
- Ambient Temperature Range480
- Temperature Endurance Test480
- Ambient Humidity Range480
- Corrosive Environments480
- Type Tests481
- Insulation481
- Creepage Distances and Clearances481
- High Voltage (Dielectric) Withstand481
- Impulse Voltage Withstand Test481
- Electromagnetic Compatibility483
- Mhz Burst High Frequency Disturbance Test483
- Damped Oscillatory Test483
- Immunity to Electrostatic Discharge483
- Electrical Fast Transient or Burst Requirements483
- Surge Withstand Capability483
- Surge Immunity Test484
- Immunity to Radiated Electromagnetic Energy484
- Radiated Immunity from Digital Communications484
- Radiated Immunity from Digital Radio Telephones484
- Immunity to Conducted Disturbances Induced by Radio Frequency Fields484
- Magnetic Field Immunity485
- Conducted Emissions485
- Radiated Emissions485
- Power Frequency485
Appendix A Ordering Options487
Appendix B Settings and Signals491

GE P24DM - Chapter Overview

Table of Contents

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