Table of Figures
Figure 1: P40L version M85 - version evolution 7
Figure 2: Key to logic diagrams 12
Figure 3: Functional Overview 13
Figure 4: Hardware architecture 32
Figure 5: Coprocessor hardware architecture 33
Figure 6: Exploded view of IED 34
Figure 7: Front panel (60TE) 37
Figure 8: Rear view of populated case 41
Figure 9: Terminal block types 42
Figure 10: Rear connection to terminal block 43
Figure 11: Main processor board 44
Figure 12: Power supply board 45
Figure 13: Power supply assembly 46
Figure 14: Power supply terminals 47
Figure 15: Watchdog contact terminals 48
Figure 16: Rear serial port terminals 49
Figure 17: Input module - 1 transformer board 49
Figure 18: Input module schematic 50
Figure 19: Transformer board 51
Figure 20: Input board 52
Figure 21: Standard output relay board - 8 contacts 53
Figure 22: IRIG-B board 54
Figure 23: Fibre optic board 55
Figure 24: Rear communication board 56
Figure 25: Ethernet board 56
Figure 26: Redundant Ethernet board 58
Figure 27: Fully populated Coprocessor board 60
Figure 28: Software Architecture 66
Figure 29: Frequency response of FIR filters 72
Figure 30: Frequency Response (indicative only) 73
Figure 31: Navigating the HMI 80
Figure 32: Default display navigation 82
Figure 33: Circuit Breaker Trip Conversion Logic Diagram (Module 63) 89
Figure 34: Ping-pong measurement for alignment of current signals 102
Figure 35: Asymmetric propogation delay times 104
Figure 36: Dual slope current differential bias characteristic 105
Figure 37: Phase Current Differential Protection logic 107
Figure 38: Capacitive charging current 112
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